Method and device for evaluating a digital signal using a digital counter with LSB signal separately applied to both counter and register

A digital counting device for evaluating a digital frequency signal (S) comprising:

• a) a first D flip-flop having the digital frequency signal (S) as an input, having a clock signal (C) as a clock input, and having an output, wherein the clock signal (C) has a frequency that is at least double a maximum frequency of the digital frequency signal (S);
• b) a second D flip-flop having the output of the first D flip-flop as an input, having the clock signal (C) as a clock input, and having a digital signal (S.sub.s) as an output;
• c) a third D flip-flop having a timing signal as an input, a clock signal (C) as a clock input, and outputting a synchronous timing signal (T.sub.s) that is synchronized to the clock signal (C);
• d) a first inverter receiving the digital signal (S.sub.s) as an input and outputting an inverted digital signal (S.sub.s);
• e) a second inverter receiving and inverting the inverted digital signal (S.sub.s), and outputting a delayed digital signal (S'.sub.s);
• f) a digital counter:
• i) receiving the inverted digital signal (S.sub.s) as an input;
• ii) evaluating the inverted digital signal (S.sub.s);
• and
• iii) outputting a plurality of N binary signals representing N binary positions;
• g) a data register receiving the synchronous timing signal as a clock input, receiving the delayed digital signal (S'.sub.s) as a first input, receiving the plurality of N binary signals as a second input, and outputting a single binary signal having a least significant binary position and a plurality of N other binary positions, wherein said delayed digital signal (S'.sub.s) represents the least significant binary position, and the plurality of N binary signals represent the plurality of N other binary positions.