Method and apparatus for recognition of a framing pattern distributed in a serial bit stream
AssigneeInternational Business Machines Corporation
InventorAlain Blanc
Life of this patent
Estimating the term…
Abstract
Method and apparatus for recognizing of a framing pattern of M single bits distributed at intervals of a fixed number, N of bits, as measured from the start of one framing bit to the start of the next, in an incoming serial bit stream. The system makes a computation following each reception of an arbitrary group of N incoming data, and after the minimum number of computation steps to distinguish between a `look-alike` framing pattern and a `true` framing pattern, points out with no ambiguity the very position of the "true" pattern within the bit stream, thus allowing synchronization over that stream.
Claims8
A method for recognizing a framing pattern of M single bits, with M being the number of bits in the framing pattern, distributed at intervals of a fixed number N of bits, with N being the number of bits as measured from the start of the framing bit to the start of the next, in an incoming serial bit stream, comprising the steps of:
- loading into each one of a plurality of first registers having multiple bits each, identical bit values equal to each one of the M bit values of said framing pattern, and
- initializing to a predetermined value the content of each one of a plurality of second registers having multiple bits each, and
- upon reception of N consecutive bits in said serial bit stream, loading the received bits into one single third register having multiple bits,
- said method being characterized in that it includes the steps of:
- performing a XORNOT logical operation between the contents of each one of said plurality of first registers and said third register, followed by an AND logical operation between the results of the latter XORNOT operation and the current contents of each one of said plurality of second registers, the final result being stored as new current contents for each one of said second registers, and
- checking the new current contents of each one of said plurality of second registers, and signalling the recognition of said framing pattern if only one binary one is left in only one of all said plurality of second registers.
In a telecommunication device, an apparatus intended for recognizing of a framing pattern of M single bits, M being the number of bits in the pattern, distributed at intervals of a fixed number, N of bits, N being the number of bits measured from the start of one frame bit to the start of the next, in an incoming serial bit stream comprising:
- a plurality of first registers having multiple bits each, and
- a plurality of second registers having multiple bits each, and
- third register of multiple bits, said apparatus being characterized in that it includes:
- means for, upon reception of N consecutive bits in said serial bit stream, loading the received bits into said third register, and awakening means performing a XORNOT logical operation between the contents of each one of said plurality of first registers and said third register, followed by an AND logical operation between the results of the latter XORNOT operation and the current contents of each one of said plurality of second registers, the final result being stored as new current contents for said plurality of second registers, and
- means for checking the new current contents of each one of said plurality of second registers to detect a framing pattern if one binary one is left in one of said plurality of second registers, wherein, if said framing pattern recognition is achieved, said apparatus provides any after-recognition apparatus implemented in said telecommunication device for synchronization purpose over said incoming serial bit stream, with:
- which bit position among the bit position available in said third register, is dedicated to bits from said framing pattern, and
- which bit position among the bit positions available in said third register, is dedicated to bits from said framing pattern, and
- which one among the bits of said framing pattern, is next to be expected in the next group of consecutive bits in the serial bit stream to be loaded into said third register.
An apparatus for recognizing a framing pattern of bits within a stream of incoming serial bits comprising:
- at least one first multibit register;
- at least one second multibit register;
- a third multibit register;
- a first means for, upon reception of N consecutive bits in said serial bit stream, loading the received bit into said third multibit register;
- awakening means for performing a XORNOT logical operation between the contents of said at least one first multibit register and said third register;
- a second means for performing a logical AND operation between the results of the latter XORNOT operation and the current contents of said at least one second multibit register with the final results being stored as a new contents in said at least one second multibit register;
- and
- means for checking the new current contents for the at least one second multibit register to detect a framing pattern if one binary one is left in the at least one second multibit register.
Dependencies are inferred from the claim text.