Multiprocessor bus debugger

An apparatus for testing over a Versa Module Europa bus, said apparatus comprising:

• a trigger source selector selecting at least a data transfer acknowledge trigger, an external trigger, an address trigger and an address count trigger;
• a reset circuit comprising a reset switch commanding an end to a test;
• a first latch responsive to said trigger source selector and toggling a bus request signal to the VME bus when said trigger source selector receives the trigger signal;
• a second latch, responsive to said reset circuit and the VME bus, first toggling a bus busy signal when a bus grant signal is received from the VME bus and second toggling a bus busy signal when said reset circuit commands an end to the test;
• a keypad;
• a controller, connected to said keypad, said trigger source selector and said second latch, wherein said controller comprises said reset circuit for commanding an end of a test;
• an address register connected to address lines of the VME bus;
• a trigger address register storing a target address;
• an address comparator connected to said trigger address register and connected to address lines of the VME bus to output a trigger to said trigger source selector when the target address in said trigger address register coincides with an address on the address lines of the VME bus;
• a counter, connected to said address comparator, to count responsive to said address comparator when the target address in said trigger address register coincides with an address on the address lines of the VME bus;
• a comparator, connected to said counter and a trigger address counter register, to output a trigger to said trigger source selector when a predetermined count is obtained;
• a write data register connected to data lines of the VME bus wherein said write data register writes data in said write data register over the VME bus to an address indicated by said address register after said trigger source selector receives a trigger signal and said first and second latches, have toggled said bus request signal;
• a read data register connected to said data lines of the VME bus wherein said read data register reads data over data lines of the VME bus from an address indicated by said address register after said trigger source selector receives a trigger signal and said first latch has toggled said bus request signal;
• and
• a display connected to at least said read data register to display the data in said read data register.

A method for testing over a multiprocessor bus, said method comprising the steps of:

• (a) selecting a trigger source by moving a movable test probe to electrically contact a position in a circuit;
• (b) toggling a bus request signal when the moveable test probe receives a trigger signal;
• (c) writing data to or reading data from the multiprocessor bus to debug the bus;
• (d) toggling the bus busy signal when a bus grant signal is received from the multiprocessor bus;
• and
• (e) toggling a bus busy signal when a reset command is detected.

An apparatus for testing over a multiprocessor bus, said apparatus comprising:

• seizing means for seizing the multiprocessor bus in response to a trigger signal;
• and
• test means, responsive to said seizing means, for testing over the multiprocessor bus when said seizing means seizes the multiprocessor bus;
• wherein said test means reads from the multiprocessor bus to test the multiprocessor bus;
• wherein said seizing means comprises:
• a trigger source selector for selecting a trigger source for said trigger signal;
• and
• an arbiter circuit for seizing the multiprocessor bus in response to the trigger signal.