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AssigneeInternational Business Machines Corporation
InventorsBarbara A. Chappell, Terry I. Chappell, Mahmut K. Ebcioglu, Stanley E. Schuster
Estimating the term…
A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address and data input latches are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus, and address and data inputs are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
A RAM structure allowing multiple read and write accesses during a machine cycle, said RAM structure being implemented on a semiconductor chip as an array of single-port static RAM cells, said array being divided into one or more sub-arrays, comprising for each sub-array;
Dependencies are inferred from the claim text.
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Arrangements for selecting an address in a digital store: multiple access memory array, e.g. addressing one storage element via at least two…
Addressing or allocation; Relocation: addressing variable-length words or parts of words
Read-write modes for single port memories, i.e. having either a random port or a serial port: using serially addressed read-write data registers
Arrangements for selecting an address in a digital store: group selection circuits, e.g. for memory block selection, chip selection, array selection
Term ended 27 Jul 2010 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention generally relates to semiconductor random access memory (RAM) devices and, more particularly, to a virtual multi-port RAM (VMPRAM) which combines multi-port RAM function with automatic port sequencing and single-port array density and speed.
2. Description of the Prior Art
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a high level block diagram of the virtual multi-port RAM according to the invention;
FIGS. 2A and 2B, taken together as FIG. 2, are a schematic illustration of a 256K semiconductor memory chip partitioned into a plurality of sub-arrays;
Referring now to the drawings, and more particularly to FIG. 1, there is shown the high level block diagram of the virtual multi-port RAM (VMPRAM) 10 according to the invention. The virtual multi-port RAM function is basically identical to that of a conventional multi-port RAM, but with built-in contention resolution. The addresses A.sub.1 to A.sub.N, data input DI.sub.1 to DI.sub.N, and control signals become valid simultaneously at the port inputs, at the beginning of the machine cycle. At the conclusion of the machine cycle, the access data is valid on the output ports DO.sub.1 to DO.sub.N, and the input data has been written into the RAM array. Unlike a conventional multi-port RAM, the VMPRAM internally contains arrays of conventional single-port RAM cells, which are cycled multiple times during a single machine cycle to service the multiple cycles. The timing for the internal multiple cycling is derived from the self-timed signals within the arrays. The internal wiring (the address and data buses) between the I/0 port storage elements and the arrays is shared by the multiple ports and is cycled in synchronism with the array cycling. Thus, the arrays and the wiring and peripheral circuitry supporting the array has a density equivalent to a fast cycling, single-port RAM.
Both the internal cycle and the read access are fast due to the use of pipelining, self-timing, and array segmentation. As will become evident with further description, in the VMPRAM 10, a pipeline latency exists for a read operation but not for a write operation. Therefore, there may be more write-only ports than read/write ports. Since the port sequencing, and data bus timing, is automatically timed from on-chip circuitry, the priority between read and write operations and between different address ports is well defined.
To provide many internally-timed chip cycles during one machine cycle, the VMPRAM according to the invention employs input-triggered, self-resetting macros in a pipelined architecture and an array of standard RAM cells (preferably complementary metal oxide semiconductor (CMOS) six-device cells). An example of the pipelined architecture as disclosed in U.S. Pat. No. 4,845,677 to Clappell et al. is described below with reference to FIGS. 2A, 2B and 3.