Program optimizing circuit and method for an electrically erasable and programmable semiconductor memory device

In an electrically erasable and programmable semiconductor memory comprising a memory cell array having a plurality of memory strings connected to a plurality of word lines and bit lines, said memory string comprising a string select transistor, a given number of memory cells and a ground select transistor, and a data bus, a program optimizing circuit comprising:

• program voltage generating means comprising a first high voltage pumping circuit for receiving a first high voltage of a first level to transfer said first high voltage to said bit lines in response to clock pulses, a latch circuit and a transfer means connected between the output node of said latch circuit and said bit lines;
• discharging means having a channel connected between said bit lines and a ground and a gate connected to a given discharge signal;
• ground connecting means having a channel connected between a common source line of said ground select transistor within said memory string and ground, and a gate connected to a program signal;
• column decoder means for outputting either one of a second high voltage of a second level and a column address signal according to said program signal;
• a plurality of column select transistors, each column select transistor having a channel connected between said data bus and said plurality of bit lines and a gate coupled to receive the alternative output signal of said column decoder means;
• data gating means for receiving external inputted data, said external inputted data being controlled by said program signal;
• and
• anti-program voltage generating means interposed between said data gating means and said data bus for receiving said second high voltage, and transferring one of said second high voltage and said external inputted data to said data bus according to an output state of said data gating means.

An electrically erasable and programmable semiconductor memory, comprising:

• a plurality of word lines and bit lines;
• a memory cell array consisting of a plurality of memory strings connected to said plurality of word lines and bit lines, said memory string comprising a string select transistor, a given number of memory cells and a ground select transistor;
• a row decoder connected to said plurality of word lines;
• a data bus and a data input/output buffer;
• a column decoder for outputting one of a second high voltage of a given level and a column address signal according to a program signal;
• a plurality of column select transistors having a plurality of channels connected between said data bus and said plurality of bit lines, and a plurality of gates coupled to receive the alternative output signal of said column decoder;
• program voltage generating means comprising a first high voltage pumping circuit for receiving a first high voltage of a first level to transfer said first high voltage to said bit lines in response to pumping clock pulses, a latch circuit and a transfer means connected between an output node of said latch circuit and said bit lines;
• discharging means having a channel connected between said bit lines and ground, and a gate connected to a given discharge signal;
• ground connecting means having a channel connected between a common source line of said ground select transistors of said memory string and ground, and a gate connected to said program signal;
• data gating means for receiving the output of said data input/output buffer and said program signal;
• and
• anti-program voltage generating means interposed between said data gating means and said data bus for receiving said second high voltage and transferring one of said second high voltage and the output data of said data input/output buffer to said data bus according to an output of said data gating means.

In an electrically erasable and programmable semiconductor memory comprising a memory cell array consisting of a plurality of memory cells connected to a plurality of word lines and bit lines, a row decoder connected to said plurality of word lines, a column decoder for receiving column address signals, a data input/output line, a data bus and data input/output buffer, and a plurality of column select transistors having a plurality of channels connected between said data bus and said plurality of bit lines, and a plurality of gates coupled to receive the output signal of said column decoder, a program optimizing method comprising the steps of:

• storing available data from said input/output buffer stored in a latch circuit, if a program signal is disabled, through a gate gating means, an anti-program voltage means, the column select transistors, the bit lines and a transfer means, said anti-program voltage generating means being interposed between said data input/output line and said data input/output buffer for pumping a second high voltage of said program signal, said data gating means being connected between said data input/output buffer and anti-program voltage generating means and controlled by said program signal;
• and
• turning off said transfer means and applying a first high voltage from a program voltage generating means to a selected bit line and applying said second high voltage to all of the gates and the channels of the column select transistors connected to the bit lines, said program voltage generating means connected to each of the bit lines and comprising a first high voltage pumping circuit, if said program signal is enabled, said latch circuit and said transfer means connected between said latch circuit and said selected bit line, said transfer means being controlled by a bit line selected signal according to said program signal.

In an electrically erasable and programmable semiconductor memory comprising a memory cell array consisting of a plurality of memory cells connected to said plurality of word lines and bit lines, said memory string comprising a string select transistor, a given number of memory cells and a ground select transistor, a row decoder connected to said plurality of word lines, a data input/output line, a data bus and a data input/output buffer, and a plurality of column select transistors having a plurality of channels being connected between said data bus and said plurality of bit lines, and a plurality of gates coupled to receive the output signal of said column decoder, a program optimizing method comprising the steps of:

• connecting to each of said bit lines a program voltage generating means comprising a first high voltage pumping circuit for receiving a first high voltage of a given level to transfer it to said bit lines in response to pumping clock pulses, a latch circuit and a transfer means connected between said latch circuit and said bit lines, said transfer means being controlled by a bit line select signal according to a program signal;
• and
• storing available data from the input/output buffer, if a program signal is disabled, into a latch circuit through a data gating means, an anti-program voltage generating means, the column select transistors, the bit lines and the transfer means, said anti-program voltage generating means being connected between said data input/output buffer and data bus and controlled by said program signal;
• ground the bit lines by turning on of the ground select transistor and turning off, if said program signal is disabled, said transfer means, said ground select transistor having a gate connected to said program signal, said transfer means controlled by a bit line select signal according to said program signal;
• and
• turning off said transfer means and applying said first high voltage from a generating means to a selected bit line and applying, if said program signal is enabled, a second high voltage to all of the gates and channels of the column select transistors connected to the bit lines, said program voltage generating means being connected to each of the bit lines.

An electrically erasable and programmable semiconductor memory device, comprising:

• a plurality of bit lines arranged in columns;
• a plurality of word lines arranged in rows;
• a memory cell array consisting of a plurality of memory strings arranged in rows and columns connected to said plurality of bit lines and said plurality of word lines, each memory string arranged in a column comprising a string select transistor, a plurality of memory cells and a ground select transistor, each ground select transistor of each memory string having a source connected to a common source line, said common source line connected to a ground connect transistor for enabling transmission of a program signal to access to said common source line;
• row decoder means coupled to said plurality of bit lines arranged in columns, for providing a first voltage signal in dependence upon reception of clock pulses to access said plurality of memory cells via a plurality of discharge transistors;
• column decoder means connected to said plurality of bit lines arranged in a column, for providing a column address signal in dependence upon reception of a second voltage signal to access to said plurality of memory cells via a plurality of column select transistors, each column select transistor having a channel connected to each bit line of said plurality of bit lines and a data bus;
• and
• anti-program voltage generator means for enabling transmission of one of said second voltage signal and a ground signal to said data bus in dependence upon reception of said second voltage signal, said clock pulses and a data gate signal, said data gate signal being responsive to said program signal.