Semiconductor memory device having test mode

A semiconductor memory device comprising:

• a memory cell array;
• control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal, said control means comprising a first buffer means for buffering said external signal and reset means responsive to a power supply for initializing said first buffer means;
• test mode designating means for controlling initiation and termination of a test operation of said memory cell array in response to said external control signal;
• and
• a second buffer means for buffering said external control signal, said test mode designating means connected to an output of said second buffer means.

A semiconductor memory device capable of performing normal mode and test mode operation, comprising:

• a memory cell array;
• control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal;
• test mode designating means for setting and resetting test mode operation of said memory cell array in response to said control means;
• said control means comprising a first buffer means comprising a plurality of inverters for buffering said external signal and a second buffer means comprising a plurality of inverters for buffering said external control signal, said second buffer means having a higher hysteresis voltage threshold level than said first buffer means;
• and
• said test mode designating means connected to an output of said second buffer means.

A semiconductor memory device comprising:

• a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns;
• a plurality of word lines formed on said substrate and corresponding to said rows of memory cells;
• a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line;
• a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation;
• a first input buffer means formed on said substrate for applying a first internal address strobe signal to said row decoder in response to an external row address strobe signal and a voltage level of a power on reset signal;
• and
• a second input buffer means formed on said substrate for generating a second internal row address strobe signal in response to said external row address strobe signal;
• and
• means for applying said second internal row address strobe signal to said test mode control means.

A semiconductor memory device comprising:

• a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns;
• a plurality of word lines formed on said substrate and corresponding to said rows of memory cells;
• a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line;
• a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation;
• a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal;
• and
• a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second bilevel internal row address strobe signal changing between a first level and a second level on a delayed basis in comparison with said first internal address strobe signal.

A semiconductor memory device comprising:

• a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns;
• a plurality of word lines formed on said substrate and corresponding to said rows of memory cells;
• a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line;
• a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation;
• a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal;
• and
• a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, a threshold voltage required for changing from a low level to a high level in said second input buffer means being higher than a threshold voltage required for changing from a low level to a high level in said first input buffer.

A semiconductor memory device comprising:

• a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns;
• a plurality of word lines formed on said substrate and corresponding to said rows of memory cells;
• a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line;
• a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation;
• a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal;
• and
• a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second input buffer means having a predetermined voltage difference between a threshold voltage required for changing said second bilevel internal row address strobe signal from a low level to a high level and a threshold voltage required for changing said second bilevel internal row address strobe signal from a high level to a low level.

A semiconductor memory device comprising:

• a memory cell array,
• internal circuit means associated with data from said memory cell array and data writing to the same,
• reset pulse generating means responsive to a power supply for generating a reset pulse initializing said internal circuit means,
• said internal circuit means operating in response to first, second and third external control signals after said reset pulse is output from said reset pulse generating means,
• test mode designating signal generating means responsive to a change in the logical level of said third external control signal from a first logical level to a second logical level when said first and second external control signals are at a predetermined logical level for generating a test mode designating signal designating a test mode,
• first external control signal buffering means for buffering said first external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means,
• second external control signal buffering means for buffering said second external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means,
• first means for buffering said third external control signal for buffering said third external control signal only when said reset pulse is not generated from said reset pulse generating means and applying the same to said internal circuit means, and
• second means for buffering said third external control signal for buffering said third external control signal at all times without being controlled by said reset pulse and applying the same to said test mode designating signal generating means.