Method and apparatus for implementing redundancy in parallel memory structures

In a memory structure comprising a plurality of arrays, and data paths connected to the memory structure for writing data into and reading data from said memory structure according to a memory structure address control signal, a method for bypassing defects detected as present in said arrays of said memory structure comprising the steps of:

• adding M spare alternate arrays to said memory structure;
• connecting the address control signal and data paths to address switches, said address switches directing the data into and from arrays identified by the address control signal;
• connecting the address switches to data switches, said data switches interleaved with one another such that the data switches may be selectively coupled to an array and an alternate array, said array and alternate array spaced M arrays apart;
• if a defect in an array is detected, changing the state of data switches which are coupled to arrays between and including the defective array and spare alternate arrays, to be coupled to alternate arrays thereby diverting data around the defective array.

In a data structure comprising a plurality of arrays, and data paths connected to the data structure for transferring data into and transferring data from said data structure according to a data structure address control signal, a method for bypassing defects detected by a controller to be present in said arrays of said data structure, said method comprising the steps of:

• connecting the address control signal and data paths to address switches, said address switches directing the data into and from arrays identified by the address control signal;
• connecting the address switches to data switches, said data switches interleaved with one another such that the data switches may be selectively coupled to an array and an alternate array, said array and alternate array spaced M arrays apart;
• providing a status switching means to be connected to each data switch, said status switching means indicating whether arrays are defective;
• connecting the controller to a first status switching means;
• connecting the status switching means through a propagating means whereby a signal received by the first status switching means is propagated through to the remaining status switching means;
• if defects in an array is detected by the controller,
• said controller sending a signal to the first status switching means identifying the location of the defective array,
• propagating the signal to the remaining status switching means through the propagating means,
• changing the state of data switches which are coupled to arrays between and including the defective array and spare arrays, to be coupled to alternate arrays thereby diverting data around the defective array.

In a data structure comprising a plurality of arrays, and data paths connected to the data structure for transferring data into and transferring data from said data structure according to a data structure address control signal, a circuit for bypassing defects detected by a controller to be present in said arrays of said data structure, said circuit comprising:

• M spare alternate arrays to be added to said data structure;
• address switches connected to the address control signal and data paths, said address switches directing the data into and from arrays identified by the address control signal;
• data switches connected to the address switches, said data switches interleaved with one another such that the data switches may be selectively coupled to an array and an alternate array, said array and alternate array spaced M arrays apart,
• status switching means connected to each data switch, said status switching means indicating whether arrays are defective, a first status switching means connected to the controller;
• propagating means connected between the status switching means, whereby a signal received by the first status switching means is propagated through to the remaining status switching means;
• such that if a defect in an array is detected, a signal is output by the controller to the first status switching means identifying the array containing the defect and the signal is propagated through the status switching means through the propagating means and the state of data switches which are coupled to arrays between and including the defective array and spare arrays are changed to be coupled to alternate arrays thereby diverting data around the defective array.

In a memory structure comprising a plurality of arrays of memory, and data paths connected to the memory structure for writing data into and reading data from said memory structure according to a memory structure address control signal, a circuit for bypassing defects detected by a controller to be present in said arrays of said memory structure, said circuit comprising:

• M spare alternate arrays to be added to said memory structure;
• address switches connected to the address control signal and data paths, said address switches directing the data into and from arrays identified by the address control signal;
• data switches connected to the address switches, said data switches interleaved with one another such that the data switches may be selectively coupled to an array and an alternate array, said array and alternate array spaced M arrays apart,
• status switching means connected to each data switch, said status switching means indicating whether arrays are defective, a first status switching means connected to the controller;
• propagating means connected between the status switching means, whereby a signal received by the first status switching means is propagated through to the remaining status switching means;
• such that if a defect in an array is detected, a signal is output by the controller to the first status switching means identifying the array containing the defect and the signal is propagated through the status switching means through the propagating means and the state of data switches which are coupled to arrays between and including the defective array and spare arrays are changed to be coupled to alternate arrays thereby diverting data around the defective array.