Static semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsKiyofumi Ochii, Shigeyuki Hayakawa
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Abstract
A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.
Claims10
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node;
- a first power source wiring arranged within the memory cell array, and connected to each memory cell so as to supply a power source potential to each memory cell;
- a second power source wiring of a low resistance to which a power source potential is supplied from the outside and which is electrically connected to the first power source wiring;
- and
- circuit means satisfying the relationship .tau. 2.gtoreq..tau. 1 wherein .tau. 1 denotes a time constant in the case of charging/discharging the memory node of each memory cell by the first power source wiring, and .tau. 2 represents a time constant in the case of charging/discharging the first power source wiring by the external power source potential supplied to the second power source wiring.
A static semiconductor memory device, comprising a memory cell array consisting of a plurality of memory cells each having a data memory node and a thin film transistor used as a load transistor and connected to one end of the memory node;
- a power source wiring connected to each memory cell included in the memory cell array so as to supply a power source potential to each memory cell;
- and
- a capacitor connected between the memory node of each memory cell and said power source wiring.
Dependencies are inferred from the claim text.