Circuit configuration for digital bit-serial signal processing

A circuit configuration for digital bit-serial signal processing, comprising:

• n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right.
• sign repetition devices each being assigned to a respective one of said input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right;
• a serial arithmetic unit connected downstream of said input shift registers for serially outputting output data words;
• m output shift registers connected downstream of said serial arithmetic unit being written in serially with the output data words;
• a control unit connected to said serial arithmetic unit, once all of the output data words have been fully written in said respective output shift registers, said control unit ending a reading of said input shift registers and the writing in of said output shift registers, for resetting said arithmetic unit to a defined initial state, and for enabling said input shift registers for writing in new input data words;
• feedback shift registers into which data words being transferred from said arithmetic unit and supplied back to said arithmetic unit are written in serially by shifting to the right and simultaneously read out, said feedback shift registers each having a length at least as long as the longest occurring data word;
• and
• other sign repetition devices assigned to said feedback shift registers, and
• a multiplexer connected upstream of said feedback shift registers being imposed upon said other sign repetition devices and subsequently upon said arithmetic unit, upon writing in of said respective feedback shift registers for a certain number of least significant bits of the data words to be transferred, and
• signs generated and shifted onward by said other sign repetition devices being equal to signs of the data words to be read out.