Time base correcting apparatus with means for inhibiting memory write and read addresses to prevent address overlap

Apparatus for use in a time base corrector of the type having memory means for storing and reading out a reproduced video signal reproduced by a rotary magnetic head from slant tracks on a magnetic tape which is transported at a desired tape running speed that may be different from a tape running speed used when recording said video signal on said tape, a write in-line address counter for generating a write in-line address signal supplied to said memory means, a write line address counter for generating a write line address signal also supplied to said memory means, means for providing a reproduced horizontal synchronizing signal from said reproduced video signal, a write clock signal generating circuit for generating a write in-line address increment clock signal and a write line address increment clock signal which are each synchronized with said reproduced horizontal synchronizing signal and which are supplied to said write in-line address counter and said write line address counter, respectively, a read in-line address counter for generating a read in-line address signal supplied to said memory means, a read line address counter for generating a read line address signal also supplied to said memory means, and a read clock signal generating circuit supplied with a reference horizontal synchronizing signal for generating a read in-line address increment clock signal and a read line address increment clock signal which are each synchronized with said reference horizontal synchornizing signal and which are supplied to said read in-line address counter and to said read line address counter, respectively, the combination comprising:

• means for generating first and second pairs of periodically recurring signal sequences derived form said reproduced horizontal synchronizing signal and said reference horizontal synchronizing signal, respectively;
• detecting means for providing a first detected output when respective signals from said first pair of sequences coincide and for providing a second detected output when respective signals from said second pair of sequences coincide;
• and
• control means for inhibiting a change of said read line address signal from said read line address counter in response to said first detected output from said detecting means and for inhibiting a change of said write line address signal from said write line address counter in response to said second detected output from said detecting means.