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US 5,204,754 AGranted
Video signal processing apparatus for restoring an interlaced video signal stored in a memory
AssigneeCanon Kabushiki Kaisha
InventorsTsutomu Fukatsu, Yoshihiro Nakatani
Life of this patent
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Abstract
An apparatus for processing an interlaced video signal having (2n+1) horizontal scanning lines (n: an integer) for one frame, which consists of two fields, is provided with a memory capable of storing at least an (n+1) horizontal scanning line portion of the video signal. The apparatus is arranged to reset the reading address of the memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods and to reset the writing address of the memory in response to the front edge of a vertical synchronizing signal included in the input video signal.
Claims12
A video signal processing apparatus comprising:
- a) A memory capable of storing at least an (n+1) horizontal scanning line portion of an interlaced video signal having (2n+1) horizontal scanning lines for one frame which consists of two fields, n being an integer:
- b) input means arranged to supply the interlaced video signal to said memory:
- c) writing address control means for controlling a writing address of said memory, said writing address control means being arranged to reset the writing address of said memory in response to a front edge of a vertical synchronizing signal included in the interlaced video signal received by said input means so that a head portion of the vertical synchronizing signal is written at a first address immediately after the resetting of the writing address;
- and
- d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address of said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.
2 more elements
A video signal reproducing apparatus comprising:
- a) reproducing means for reproducing from a recording medium an interlaced video signal having (2n+1) horizontal scanning lines for each frame which consists of two fields, a being an integer;
- b) a memory arranged to receive the video signal reproduced by said reproducing means and capable of storing at least an (n+1) horizontal scanning line portion of the video signal:
- c) writing address control means for controlling a writing address of said memory, said writing address control means being arranged to reset the writing address of said memory in response to a front edge of a vertical synchronizing signal included in the interlaced video signal reproduced by said reproducing means so that a head portion of the vertical synchronizing signal is written at a first address immediately after the resetting of the writing address;
- and
- d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address to said memory alternately at an interval of n horizontal scanning periods and at an interval of (n+1) horizontal scanning periods.
2 more elements
A video signal processing apparatus comprising:
- a) a memory capable of storing a larger portion than one field portion of an interlaced video signal;
- b) input means arranged to supply the interlaced video signal to said memory;
- c) writing address control means for controlling a writing address of said memory so that a head portion of a vertical synchronizing signal of the interlaced video signal is written at a first address immediately after resetting the writing address;
- and
- d) reading address control means for controlling a reading address of said memory so that a larger portion than the one field portion of the interlaced video signal and a smaller portion than the one field portion of the interlaced video signal are alternately read out from said memory.
2 more elements
A video signal processing apparatus comprising:
- a) a memory capable of storing a larger portion than one field portion of an interlaced video signal:
- b) input means arranged to supply the interlaced video signal to said memory:
- c) writing address control means for controlling a writing address of said memory so that two head portions of vertical synchronizing signals of the interlaced video signal are written in said memory;
- and
- d) reading address control means for controlling a reading address of said memory, said reading address control means being arranged to reset the reading address of said memory so that a portion including the two head portions of vertical synchronizing signals and a portion including zero or only one head portion of a vertical synchronizing signal are alternately read out from said memory.
2 more elements
Dependencies are inferred from the claim text.