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US 5,204,678 AGranted
Dual-ranked time-interval conversion circuit
AssigneeTektronix, Inc.
InventorClark P. Foley
Life of this patent
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AssigneeTektronix, Inc.
InventorClark P. Foley
Estimating the term…
A dual-ranked time-interval conversion circuit. Two time trap circuits are employed to convert the time interval between a logic level transition of a first signal and a logic level transition of a second signal to an analog or digital signal representative of that time interval. Each time trap circuit employs a delay line for receiving and propagating the first signal and a series of taps and respective storage elements along the delay line for detecting and storing the logic level of the delay line at each tap at the time of receipt of a second signal. A first time trap circuit is employed to measure the time interval in course quanta of time and a second time trap circuit is employed to measure in fine quanta of time the time difference between the actual first signal-to-second signal time interval and the coarse measurement of that interval. A nulling circuit is provided for applying a delayed strobe signal to the second time trap circuit within a predetermined period of time following receipt of the first signal. This time is preferably equal to two coarse time quanta to allow for quantizing error. Delay circuits are provided to compensate for signal propagation delay through circuit devices. The outputs of the first and second time trap circuits are applied to a digital-to-analog conversion circuit or to a digital decoding circuit for producing an analog or digital output, respectively.
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
The conversion circuit of claim 3, wherein said memory means comprises a multi-element digital latch, the data inputs of said latch corresponding to the element inputs of said memory means and the data outputs corresponding to said element outputs of said memory means.
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
The conversion circuit of claim 7, further comprising variable delay means, connected between an output disposed a predetermined distance along said delay line and said second time trap circuit, for delaying application of said first signal to said second time trap circuit, which delay is calibrated to synchronize said first signal with said delayed strobe signal applied by said nulling circuit.
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
The conversion circuit of claim 11, wherein said coarse quanta of time D(c) are equal to the total delay time of said delay line of said first time trap circuit divided by the number M of memory means storage elements of said first time trap circuit and the propagation rate of said delay line of said second time trap circuit is chosen so that said fine quanta of time D(f)=D(c).times.2/N, where N is the number of storage elements of said second memory means of said second time trap circuit.
The conversion circuit of claim 13, further comprising nulling memory means electrically disposed between said memory means of said first time trap circuit and said nulling delay line for storing said representations of signal levels provided by said outputs of said memory means of said first time trap circuit and applying said representations to said nulling delay line, said nulling memory means having a plurality of distinct storage elements, respective element inputs connected to respective element outputs of said memory means of said first time trap circuit, corresponding element outputs connected to said nulling delay line and a strobe input for receiving said second signal.
The conversion circuit of claim 15, wherein said output means comprises a summing amplifier that translates the digital data provided by said memory means of said first and second time trap circuits into a voltage proportional to said time interval.
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
The conversion circuit of claim 19, further comprising fixed delay means, connected to said transfer means, for delaying by a fixed amount of time, application of said representation of the logic level of said first signal detected by said first time trap circuit to said nulling delay line, which amount of time is at least equal to the amount of time necessary for said transfer means to receive and produce said representation at settled logic levels for application to said nulling delay line.
A conversion circuit for converting a time interval between logic level transitions of a first signal and a second signal into a third signal representative of said time interval, comprising:
Dependencies are inferred from the claim text.