Circuit arrangement for frequency conversion of a digital signal

A circuit arrangement for conversion of a digital data signal (D.sub.in) having a first clock frequency (T.sub.1) into a signal having a second clock frequency (T.sub.2), comprising an interpolator/decimator which includes a series of successively connected input registers for the data signal, each register comprising a clock input for a register clock signal, a data input for the data signal, and a data output which is coupled to an input of arithmetic circuits for calculating a linear combination of output signals, characterized in that at least one multiplexer is provided between an input register and the arithmetic circuits, a first input of the multiplexer being coupled to a data output of an input register, a second input of the multiplexer being coupled, via a first register, to said data output and an output of the multiplexer being coupled to an input of a second register, said first register comprising a clock input which is coupled to the output of an inverter present for applying an inverted first clock signal to said first register, said second register comprising a clock input for a clock signal of the second clock frequency (T.sub.2), said circuit arrangement furthermore comprising a control circuit, an output of which is coupled to a control input of the multiplexer in order to apply a control signal (M.sub.x) thereto so that the output of the multiplexer is connected to that one input of the first and second inputs of the multiplexer that receives a stable signal during writing of data into the second register.