US 5,204,638 A · Intrinsic offset recovery circuit particularly for amplifiers

Abstract

Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.

Claims18

Dependent claims

In an amplifier circuit having an input differential amplifier having a first PNP transistor, a second PNP transistor, a third NPN transistor, a fourth NPN transistor, a first constant-current source, and a unitary-gain output stage, an intrinsic offset recovery circuit connected between said input differential amplifier and said unitary-gain output stage, comprising a gain stage having a fifth NPN transistor connected to the output of said input differential amplifier and to a sixth NPN transistor and to a seventh PNP transistor, said seventh transistor being connected to sixth transistor, said seventh transistor and said sixth transistor connected to said unitary-gain output stage.

An amplifier circuit for operation between first and second voltage supplies in an integrated circuit, said amplifier circuit comprising

an input differential stage having a first current source connected to said first voltage supply, first and second current sinks connected to said second voltage supply, a current through said first current sink mirroring a current through said second current sink, first and second bipolar transistors, each bipolar transistor connected between said first current supply, and said first and second current sinks respectively, said first and second bipolar transistors having first and second base terminals respectively forming first and second input terminals to said input differential stage;
an output stage having an input terminal and an output terminal, said output terminal forming an output terminal for said amplifier circuit;
and
a stage intermediate said input differential stage and said output stage, said intermediate stage having second and third current sources each connected to said first voltage supply, third and fourth bipolar transistors, and a resistive means connected to said second voltage supply, said input terminal of said output stage connected to said third current source, said third bipolar transistor connected between said second current source and said resistive means, said third bipolar transistor having an input terminal connected to a node between said first bipolar transistor and said first current sink, said fourth bipolar transistor connected between said input terminal of said output stage and said second voltage supply, said fourth bipolar transistor having an input terminal connected to a node between said third bipolar transistor and said resistive means;
whereby a current through said third bipolar transistor is substantially decoupled from a current through said fourth bipolar transistor so that said intermediate stage operates as an intrinsic offset recovery circuit for said input differential stage.

2 more elements

Dependencies are inferred from the claim text.

Intrinsic offset recovery circuit particularly for amplifiers

Life of this patent

Intrinsic offset recovery circuit particularly for amplifiers

Life of this patent

Abstract

Claims18