Combined sense amplifier and latching circuit for high speed roms

A combined sense amplifier and latching circuit comprising:

• an input terminal for receiving an input signal;
• means for generating a gating signal;
• a gated-loop master latch connected to said input terminal having a first control device in said master latch loop, said first control device being controlled by said gating signal;
• and
• a gated-loop slave latch having a second control device in said slave latch loop, said second control device being controlled by said gating signal, said slave latch being alternately connected in series with and isolated from said master latch by a third control device controlled by said gating signal and
• a reference voltage generator for supplying a reference voltage and wherein said master latch includes first and second cascaded inverters having a common node coupled therebetween, said first and second inverters being biased between a first supply voltage and a second supply voltage in a first mode of operation and between a first supply voltage and said reference voltage in a second mode of operation, said first and second modes of operation being controlled by the value of said gating signal, and the magnitude of said reference voltage being less than the magnitude of said first supply voltage.

A circuit for sensing data contained in an integrated memory circuit comprising:

• a multiplexer circuit for receiving data from said memory circuit and connecting data signals to an output node;
• a restore circuit for restoring data at said output node to a high state;
• an input terminal connected to said output node for receiving data signals therefrom;
• means for generating a gating signal;
• a gated-loop master latch connected to said input terminal having a first control device in said master latch loop, said first control device being controlled by said gating signal;
• a gated-loop slave latch having a second control device in said slave latch loop, said second control device being controlled by said gating signal, said slave latch being alternately connected in series with and isolated from said master latch by a third control device controlled by said gating signal;
• a slave latch output terminal and an output driver circuit connected to said slave latch for supplying an output signal to said slave latch output terminal;
• a pair of output data terminals and an output data latch circuit connected to said slave latch output terminal for delivering output data to said output data terminals and,
• a reference voltage generator for supplying a reference voltage and wherein said master latch includes first and second cascaded inverters having a common node coupled therebetween, said first and second inverters being biased between a first supply voltage and a second supply voltage in a first mode of operation and between a first supply voltage and said reference voltage in a second mode of operation, said first and second modes of operation being controlled by the value of said gating signal, and the magnitude of said reference voltage being less than the magnitude of said first supply voltage.