Output buffer circuit and method of operation thereof with reduced power consumption

An output buffer circuit comprising:

• an output terminal for producing an output signal;
• charging means responsive to an input signal for charging said output terminal;
• discharging means responsive to the input signal for discharging said output terminal;
• charge storing means for storing charge;
• switching means for supplying charge from said charge storing means to said output terminal during charging by said charging means and fro supplying charge from said output terminal to said charge storing means during discharging by said discharging means;
• control means for switching said switching means in response to the input signal,
• said charging means comprising a first field effect device of a first conductive channel type connected between a first power supply node and said output terminal,
• said discharging means comprising a second field effect device of a second conductive channel type connected between a second power supply node and said output terminal,
• said charge storing means comprising capacitance means connected to said second power supply node,
• said switching means comprising a third field effect device of a second conductive channel type connected between said capacitance means and said output terminal,
• said control means comprising
• means for turning on said first and second field effect devices sequentially prior to charging, and turning on said first field effect device and turning off said second and third field effect devices, and for turning off said first and second field effect devices and turning on said third field effect device prior to discharge, and subsequently turning on said second field effect device and turning off said first ad third field effect devices.

A method of operation of an output buffer circuit for driving a load in response to an input signal comprising the steps of:

• discharging a load in response to setting a first logic level of said input signal;
• and
• charging a load in response to setting a second logic level of said input signal;
• said discharging step comprising the steps of supplying charge from said load to charge storing means in response to setting the first logic level of said input signal, and supplying charge from said load to the ground terminal in response to a signal delayed by a first predetermined period with respect to setting the first logic level of said input signal,
• said charging step comprising the steps of supplying charge from said storing means to said load in response to setting the second logic level of said input signal and supplying charge form a power supply terminal to charge storage means in response to a signal delayed by second predetermined period with respect to setting the second logic level of said input signal.

An output buffer circuit, comprising:

• a first field effect transistor responsive to an input signal and connected between a power supply node and an output node,
• a second field effect transistor responsive to the input signal and connected between a ground potential node and said output node,
• a third field effect transistor having a first electrode connected to said output node, a second electrode, and a control electrode for receiving a control signal,
• a capacitance element connected between the second electrode of said third field effect transistor and said ground potential node, and
• a control signal generating means responsive to said input signal for generating said control signal delayed with respect to said input signal.