US 5,204,557 A · Digital signal level translator

Abstract

A low static power, digital signal level translator for translating an unbalanced digital signal to a balanced digital signal with a greater dynamic signal range includes two complementary MOSFET latches and a complementary MOSFET output buffer amplifier. The two latches each receive an unbalanced digital input signal (e.g. with TTL voltage levels) and translate it to a second unbalanced digital signal and an asymmetrically balanced digital signal. The symmetrically biased, output buffer amplifier receives these signals and produces therefrom a symmetrically balanced digital output signal with a greater dynamic signal range (e.g. with .+-.10 volt levels). Various embodiments include two gate-driven complementary MOSFET latches, two source-driven complementary MOSFET latches or a combination of gate-driven and source-driven complementary MOSFET latches, each of which includes a pair of cross-coupled complementary MOSFET totem-pole amplifiers, for providing the second unbalanced digital signal and the asymmetrically balanced digital signal. Each embodiment further includes a complementary MOSFET totem-pole output buffer amplifier as the symmetrically biased, output buffer amplifier for providing the symmetrically balanced digital output signal.

Claims14

Dependent claims

A digital signal level translator for translating an unbalanced digital signal to a balanced digital signal, said digital signal level translator comprising:

first translator means for receiving and translating a first unbalanced digital signal to a second unbalanced digital signal, wherein said first unbalanced digital signal has a first unbalanced dynamic signal range bounded by a first level and a reference level, and wherein said second unbalanced digital signal has a second unbalanced dynamic signal range bounded by a second level and said reference level;
second translator means for receiving and translating said first unbalanced digital signal to a first balanced digital signal, wherein said first balanced digital signal has a first balanced dynamic signal range bounded by said first level and a third level;
and
output buffer means for receiving said second unbalanced digital signal and said first balanced digital signal, and for providing a second balanced digital signal, wherein said second balanced digital signal has a second balanced dynamic signal range bounded by said second level and said third level;
wherein said first and second levels have a first polarity relative to said reference level, and said third level has a second polarity relative to said reference level.

2 more elements

A digital signal level translation method for translating an unbalanced digital signal to a balanced digital signal, said digital signal level translation method comprising the steps of:

receiving a first unbalanced digital signal having a first unbalanced dynamic signal range bounded by a first level and a reference level;
translating said first unbalanced digital signal to a second unbalanced digital signal having a second unbalanced dynamic signal range bounded by a second level and said reference level;
translating said first unbalanced digital signal to a first balanced digital signal having a first balanced dynamic signal range bounded by said first level and a third level;
combining said second unbalanced digital signal and said first balanced digital signal to provide a second balanced digital signal having a second balanced dynamic signal range bounded by said second level and said third level;
wherein said first and second levels have a first polarity relative to said reference level, and said third level has a second polarity relative to said reference level.

2 more elements

Dependencies are inferred from the claim text.

Digital signal level translator

Life of this patent

Digital signal level translator

Life of this patent

Abstract

Claims14