Logic array having high frequency internal clocking
AssigneeGazelle Microcircuits, Inc.
InventorsAndrew C. Graham, Michael G. France, Robert C. Burd, Mark E. Fitzpatrick
Life of this patent
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Abstract
A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.
Claims29
A state machine structure comprising:
- logic array means having input leads and output leads;
- at least one register means having input terminals coupled to said output leads of said logic array means and having output terminals coupled to said input leads of said logic array means;
- and
- clock generating means for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means;
- wherein said clock generating means incorporates a phase-locked loop having first and second inputs, and having said reference signal coupled to said first input of said phase-locked loop, and an output terminal of said register means coupled to said second input of said phase-locked loop.
A monolithic structure comprising:
- a state machine having one or more input terminals and a plurality of output terminals;
- at least one register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals;
- and
- a phase-locked loop clock generating means to supply a feedback signal for comparison with a reference signal;
- one of said output terminals of said register means coupled to an input of said phase-locked loop clock generating means, said register means having an associated clock input terminal coupled to an output of said phase-locked loop clock generating means.
A circuit comprising:
- a clock generating means having one or more input leads and one or more output leads, at least one of said input leads being coupled for receiving an externally generated periodic reference signal, and outputting one or more clock signals on said output leads;
- and
- an output means having one or more input leads coupled to at least one of said output leads of said clock generating means and outputting a plurality of individually controllable signals on one or more output leads of said output means which transition at a time referenced to transitions of said reference signal regardless of any internal propagation delays of said circuit;
- wherein said plurality of individually controllable signals are phase-aligned or selectively phase-shifted with said externally generated periodic reference signal.
A circuit whose output signals are made to transition at a time reference to a time of transition of an externally generated reference signal applied to said circuit regardless of any internal propagation delays of said circuit, said circuit comprising:
- means for receiving an externally generated periodic reference signal and a feedback signal and for providing an output clock signal at a frequency different than said reference signal;
- logic array means for receiving input signals and for performing logical functions on said input signals and for providing results of said logical functions at output terminals of said logic array means;
- and
- one or more register means, at least one of said register means having one or more input terminals coupled to said output terminals of said logic array means and having one or more output terminals coupled to inputs of said logic array means, at least one of said register means including an output terminal for providing said feedback signal, and at least one of said register means having a clock input terminal coupled to receive said output clock signal.
A monolithic structure comprising:
- a state machine having one or more input terminals and a plurality of output terminals;
- at least one register means, at least one of said register means having input terminals coupled to said output terminals of said state machine and having a plurality of output terminals;
- and
- clock generating means incorporating a phase-locked loop for generating a clock signal having a frequency different than a reference signal applied to said clock generating means, said clock generating means having an output coupled to a clock input terminal of one or more of said register means,
- one of said output terminals of said register means being coupled to an input of said clock generating means for supplying a feedback signal to be compared with said reference signal.
Dependencies are inferred from the claim text.