US 5,204,280 AGranted

Process for fabricating multiple pillars inside a dram trench for increased capacitor surface

AssigneeInternational Business Machines Corporation

InventorsSang H. Dhong, John C. Malinowski

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Abstract

A method is disclosed for fabricating a DRAM trench capacitor with multiple-pillars inside the trench for increased surface area. A thin pad oxide of a few tens of nonometers is grown on a silicon substrate. A layer of silicon nitride is deposited and another layer of oxide is then deposited. This provides the ONO stack. Then a layer of polysilicon, a layer of nitride, and a layer of large-grained polysilicon are deposited sequentially. Then, a trench is defined by a lithographic mask and the exposed large-grained polysilicon is etched in CF.sub.4. Since CF.sub.4 etches the polysilicon and nitride 20 at almost the same rates, the topographical features existed in the polysilicon layer is copied to the nitride layer. The nitride layer is partially etched. The RIE etching gas is then changed to a mixture of HBR, SiF.sub.4, Helium, and NF.sub.3 which gives a very directional polysilicon etching with a good selectivity to nitride and a very high selectivity to oxide. Consequently, the topographical features on the nitride layer is enhanced and is transferred to the polysilicon layer which is used as a mask to etch the oxide nitride and pad oxide to form pillars.

Claims6

Dependent claims

A method of fabricating semiconductor memory devices with trench capacitors having increased surface areas comprising the steps of:

step 1) forming a first plurality of stacked layers of material on a substrate surface;
step 2) forming a second plurality of stacked layers of material on said first plurality of stacked layers wherein the uppermost layer of said second plurality of layers has an irregular surface;
step 3) etching a selected region of said uppermost layer of said second plurality of stacked layers and partially etching said next to uppermost layer of said second plurality of stacked layers to form a trench wherein the irregular surface of said uppermost layer is replicated in the etched surface of said partially etched next to uppermost layer;
step 4) directionally etching said next to uppermost layer with a selective etchant that etches said uppermost layer faster than said next to uppermost layer to remove said next to uppermost layer and form spaced pillars of polysilicon from said first uppermost layer;
step 5) using said spaced pillars of said uppermost layer as a mask, etching said second plurality of stacked layers to form pillars on the surface of said substrate within said trench composed of layers of said first and second plurality of said stacked layers.

2 more elements

Dependencies are inferred from the claim text.