Analog to digital converter

A circuit comprising a plurality of circuit cells, each of said circuit cells having a first input node, a second input node, a first output node and a second output node, each of said circuit cells comprising:

• a first resistance coupled between the first input node and the second input node;
• a plurality of switch means;
• and
• a second resistance, the second resistance being coupled to said plurality of switch means for being switchably coupled between, in a first state, the first input node and the first output node, and, in a second state, between the second input node and the second output node, and wherein in the first state the second output node is switchably coupled to the second input node and in the second state the first output node is switchably coupled to the first input node.

An analog to digital logarithmic converter circuit for converting an analog input signal to an (n) bit digital output that is a base 2 logarithmic expression of the analog input signal, the circuit comprising:

• (n) circuit cells, each of said (n) circuit cells having a first input node, a second input node, a first output node and a second output node, said (n) circuit cells being serially coupled together in such a manner that said second output node of a first circuit cell is coupled to said first input node of said second circuit cell, each of said (n) circuit cells outputting one digital bit of the base 2 logarithmic expression, (n) being the order of the digital output bit wherein an (n)th circuit cell outputs an (n)th digital output bit, each of said (n) circuit cells comprising:
• means for comparing an analog input signal that is coupled to said first input node to a reference signal that is coupled to said second input node, a magnitude of said reference signal being a function of the order of a corresponding digital output bit, said comparing means having an output coupled to said first output node for providing a bit of the (n) bit digital output, a state of the bit indicating whether a magnitude of the analog input signal is greater than or less than the magnitude of the reference signal;
• means for providing a first analog signal having a magnitude that is a function of the analog input signal multiplied by a predetermined factor that is a function of the order (n) of the digital output bit to which said circuit cell corresponds to;
• means for providing a second analog signal having a magnitude equal to the magnitude of the analog input signal;
• and
• switching means, coupled to the output of said comparing means and responsive to the state of the bit output thereby, for switchably coupling either the first analog signal or the second analog signal to the second output node.

A synchronous converter cell, comprising:

• edge-triggered sample and hold means, said edge-triggered sample and hold means comprising,
• means for comparing an analog input signal to a first reference signal, said comparing means having an output for providing a signal that indicates whether a magnitude of said analog input signal is greater than or less than said first reference signal;
• digital delay means having an input coupled to the output of said comparing means, said digital delay means having a clock input coupled to a clock signal for storing the output of said comparing means on an edge of the clock signal, said digital delay means further having an output expressive of a time-delayed version of the output of said comparing means;
• and
• analog delay means, having an input coupled to said analog input signal, said analog delay means having a clock input coupled to the clock signal for storing the analog input signal on the same edge of the clock signal that said digital delay means stores the output of said comparing means, said analog delay means having an output expressive of a time-delayed version of the analog input signal.

The synchronous converter cell as set forth in claim 35 wherein said edge-triggered sample and hold means includes:

• first switch means having a first input coupled to said analog input signal;
• first sample and hold means having an input and an output, the input being coupled to a first output node of said first switch means, said first sample and hold means outputting a first sampled analog signal;
• second sample and hold means having an input and an output, the input being coupled to a second output node of said first switch means, said second sample and hold means outputting a second analog signal;
• second switch means having a first input node coupled to an output of said first sample and hold means and a second input node coupled to an output of said second sample and hold means, said second switch means having an output node;
• and
• means for generating a first clock signal and a second clock signal, said first clock signal being out-of-phase with said second clock signal, said first clock signal and said second clock signal activating said first switch means and said second switch means whereby when said analog input signal is coupled to the input of said first sample and hold means, the output of said second sample and hold means is coupled to said output node of said second switch means, and when said analog input signal is coupled to the input of said second sample and hold means, the output of said first sample and hold means is coupled to said output node of said second switch means.