RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output

A method of executing an instruction on a reduced instruction set computer having a multi-bit extension appended to the data and instruction registers, wherein the multi-bit extension includes a tag field for identifying the data type of the data words process therethrough, comprising the steps of:

• storing in a memory a plurality of instruction words each having a full precision instruction portion and a multi-bit extension having a tag field;
• retrieving an instruction word from said memory;
• storing said instruction word in an instruction register coupled to said memory;
• retrieving a first data word having a data portion and a tag field from a first data register and applying said data portion to the first input of an arithmetic logic unit;
• retrieving a second data word having a data portion from a second data register or from said instruction register and applying said data portion to the second input of said arithmetic logic unit;
• performing a computation on said data portions of said first and second data words as determined by said full precision instruction portion of said instruction word and providing a resulting data word;
• selecting between said tag field of said first data word and said tag field of said instruction word as determined by a control signal in said tag field of said instruction word;
• and
• combining said resulting data word of the computation with said selected tag field for storage in a third data register.

An integrated microprocessor having a reduced instruction set computer architecture, comprising:

• first means having a bi-directional port and first and second outputs and including a plurality of registers for storing data words therein, said data words including a full precision data portion and a tag field for identifying the data type thereof, wherein said first output provides a separate data portion and tag field of a first data word and said second output provides a separate data portion and tag field of a second data word;
• second means having first and second inputs respectively coupled to said first and second outputs of said first means for performing arithmetic computation on said data portions of said first and second data words and providing a resulting data word having a data portion at a first output which is applied at said bi-directional port of said first means;
• third means for storing a plurality of instruction words each having a full precision instruction portion and a tag field;
• fourth means coupled to said third means for receiving an instruction word;
• and
• fifth means for selecting between said tag field of said instruction word applied at a first input and said tag field of said first data word applied at a second input under control of predetermined bits from said tag field of said instruction word and providing at an output one of said tag fields applied at said first and second inputs, wherein said tag field provided at said output is applied at said bi-directional port of said first means and combined with said data portion of said resulting data word of said second means for storage into said first means.