Fourth order digital delta-sigma modulator

A digital delta-sigma modulator having at least two stages of integration, the at least two stages of integration comprising:

• an adder having two inputs;
• a plurality of data registers connected in a serial configuration, the input of the first of said data registers connected to an output of said adder, and an output of the last of said data registers connected to one input of said adder;
• a multiplexer having two inputs and one output, said output connected to the other input of said adder, one of said inputs of said multiplexer connected to an external data signal and the other of said inputs connected to the output of one of said registers;
• an output device for selecting the output of one of said registers for output therefrom;
• and
• a timing device for sequencing the output of said adder through said registers as an accumulated value and, at a select time, controlling said multiplexer to input said external data signal to the other input of said adder for summation with the output of the last of said data registers.

A method for performing a delta-sigma conversion in a digital-to-analog converter by receiving an m-bit digital word at a sampling rate and converting it to an m'-bit digital word, m' being less than m, comprising the steps of:

• receiving as a digital input the m-bit digital word and a feedback value and summing the two values together to provide a first output sum;
• performing n stages of integration on the output sum;
• scaling the output after each integration step for output along an associated feed-forward path;
• summing each of the outputs of the feed-forward paths at an output summing junction to provide a second output sum;
• and
• quantizing the second output sum to generate the m'-bit output of the delta-sigma conversion operation;
• the step for performing the n-integration stages comprising:
• providing an adder having two inputs;
• providing a data register medium for temporarily storing an output of the adder and having at least one register that is operable to present on an output thereof more than one accumulated value at different times for a given digital input,
• multiplexing the operation of the adder for each word received in the input summing operation to generate a first output sum and performing n summations with the value of the digital input and previously stored values in the data register medium to perform the operation of each stage of integration and storing the results in the data register medium as accumulated values, and
• selecting the accumulated values for input to the output summing junction after generation thereof in accordance with the operation of the associated integration stages thereof, the step of selecting also operable to perform the associated scaling operations.

A method for performing a digital delta-sigma modulation and performing at least two stages of integration, the step of performing at least two stages of integration comprising the steps of:

• providing an adder having two inputs, each for receiving an input value;
• providing a plurality of data registers;
• configuring the data registers in a serial configuration;
• summing the input values on the inputs to the adder and inputting as stored sum values the sum provided therefrom into the input of the first of the data registers in the serial configuration;
• sequencing the sum values stored in the data registers through the serial configuration of data registers;
• outputting the value from the last of the data registers and inputting it to one input of the adder;
• inputting an external data signal into the other input of the adder for one cycle of the sequencing operation of the registers;
• and
• selecting the output of one of the data registers for input to the other input of the adder when the external data signal is not connected to the other input of the adder.