# US 5,196,376 A · Laser lithography for integrated circuit and integrated circuit interconnect manufacture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,196,376 A - Document ID: US5196376A - Status: Granted - Kind: A - Application number: 07/662,748 - Filed: 1991-03-01 - Granted: 1993-03-23 - Earliest claimed: 1991-03-01 - Assignees: Polycon Corporation - Inventors: John J. Reche - Web page: https://patentgrep.com/patent/US5196376A ## CPC - H10P 14/683: {carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC} - H05K 3/061: {Etching masks} - H10P 50/71: {using masks for conductive or resistive materials} - H10P 76/20: of masks comprising organic materials - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H05K 3/0041: {by plasma etching} - H05K 2201/0166: Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching - H05K 2201/0179: Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor - H05K 2203/0554: Metal used as mask for etching vias, e.g. by laser ablation - H05K 2203/107: Using laser light - Y10S 438/94: Laser ablative material removal - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ## Abstract A laser lithography process for semiconductor interconnect and semiconductor manufacture having the advantages of non-contact printing processes and being much faster than prior art laser lithography processes is disclosed. In accordance with the process, a metal layer to be patterned either for use as a patterned metal layer or as a mask for patterning a layer therebelow, such as a think polyimide layer, is first coated with a very thin layer of polymer evaporated as a monomer using a vapor deposition process. This provides a very thin layer of polymer over the metal layer, which thin polymer layer is readily and quickly patterned by laser to provide a mask for the subsequent chemical etching of the metal layer. The vapor deposited polymer layer, while being very thin and thus readily removed by laser, is also substantially fault free, thereby providing a high-quality mask for the chemical etching process free of any possible damage from ordinary sources such as mask aligners, etc., yet being readily removed when desired such as by way of example, by plasma etching thereof. Various methods and applications are disclosed. ## Claims ### Claim 1 A method of patterning a layer of metal during the fabrication of a microelectronic circuit comprising the steps of: (a) vapor depositing a layer of polymer having a thickness of approximately 200 to 1000 Angstroms onto the layer of metal by vaporizing a corresponding monomer in a vacuum and allowing the same to deposit onto the layer of metal substantially as a polymer; (b) patterning the thin layer of polymer to expose corresponding areas of the metal layer therebeneath by removing the same in selected areas with a laser; and, (c) selectively etching the exposed areas of the metal layer to pattern the metal layer in accordance with a pattern defined by the thin layer of polymer. ### Claim 2 (depends on 1) The method of claim 1 wherein the thin layer of polymer is a paraxylylene compound. ### Claim 3 A method of forming a patterned layer of metal during the fabrication of a microelectronic circuit comprising the steps of: (a) depositing the layer of metal onto a partially completed microelectronic circuit; (b) vapor depositing a layer of polymer having a thickness of approximately 200 to 1000 Angstroms onto the layer of metal by vaporizing a corresponding monomer in a vacuum and allowing the same to deposit onto the layer of metal substantially as a polymer; (c) pattering the thin layer of polymer to expose corresponding areas of the metal layer therebeneath by removing the same in selected areas with a laser; and, (d) chemical etching the exposed areas of the metal layer to pattern the metal layer in accordance with a pattern defined by the thin layer of polymer. ### Claim 4 (depends on 3) The method of claim 3 wherein the thin layer of polymer is a paraxylylene compound. ### Claim 5 A method of patterning a thick layer of polymer during the fabrication of a microelectronic circuit comprising the steps of: (a) depositing a layer of metal onto the thick layer of polymer; (b) vapor depositing a layer of polymer having a thickness of approximately 200 to 1000 Angstroms onto the layer of metal by vaporizing a corresponding monomer in a vacuum and allowing the same to deposit onto the layer of metal substantially as a polymer; (c) patterning the thin layer of polymer to expose corresponding areas of the metal layer therebeneath by removing the same in selected areas with a laser; (d) chemical etching the exposed areas of the metal layer to remove parts of the metal layer to expose areas of the thick polymer layer therebeneath in accordance with the pattern defined by the thin layer of polymer; and, (e) plasma etching the thick layer of polymer in the regions exposed by removal of the metal layer therefrom. ### Claim 6 (depends on 5) The method of claim 5 wherein the thick layer of polymer is a polyimide layer. ### Claim 7 (depends on 5, 6) The method of claim 5 or 6 wherein the thin layer of polymer is a paraxylylene compound. ### Claim 8 (depends on 5, 6) The method of claim 5 or 6 wherein the thin layer of polymer is a paraxylylene compound having a thickness of approximately 200 to 1000 Angstroms. ### Claim 9 A method of forming a patterned thick layer of polymer during the fabrication of a microelectronic circuit comprising the steps of: (a) forming a thick layer of polymer on a partially completed microelectronic circuit; (b) depositing a layer of metal onto the thick layer of polymer; (c) vapor depositing a thin layer of polymer onto the layer of metal by vaporizing a corresponding monomer in a vacuum and allowing the same to deposit onto the layer of metal substantially as a polymer; (d) patterning the thin layer of polymer to expose corresponding areas of the metal layer therebeneath by removing the same in selected areas with a laser; (e) chemical etching the exposed areas of the metal layer to remove parts of the metal layer to expose areas of the thick polymer layer therebeneath in accordance with the pattern defined by the thin layer of polymer; and, (f) plasma etching the thick layer of polymer in the regions exposed by removal of the metal layer therefrom. ### Claim 10 (depends on 9) The method of claim 9 wherein the thick layer of polymer is a polyimide layer. ### Claim 11 (depends on 9, 10) The method of claims 9 or 10 wherein the thin layer of polymer has a thickness of approximately 200 to 1000 Angstroms. ### Claim 12 (depends on 9, 10) The method of claim 9 or 10 wherein the thin layer of polymer is a paraxylylene compound. ### Claim 13 (depends on 9, 10) The method of claim 9 or 10 wherein the thin layer of polymer is a paraxylylene compound having a thickness of approximately 200 to 1000 Angstroms. ### Claim 14 A method of patterning a layer during the fabrication of a microelectronic circuit comprising the steps of: (a) vapor depositing a thin layer of polymer onto the layer to be patterned by vaporizing a corresponding monomer in a vacuum and allowing the same to deposit onto the layer to be patterned substantially as a polymer; (b) patterning the thin layer of polymer to expose corresponding areas of the layer to be patterned therebeneath by removing the same in selected areas with a laser; and, (c) selectively etching the exposed areas of the layer to be patterned to pattern the layer in accordance with a pattern defined by the thin layer of polymer. ### Claim 15 (depends on 14) The method of claim 14 wherein the thin layer of polymer has a thickness of approximately 200 to 1000 Angstroms. ### Claim 16 (depends on 14) The method of claim 14 wherein the thin layer of polymer is a paraxylylene compound. ### Claim 17 (depends on 14) The method of claim 14 wherein the thin layer of polymer is a paraxylylene compound having a thickness of approximately 200 to 1000 Angstroms.