A parallel processing system including a virtual processing instruction and address generator, for generating a plurality of processor cell instructions and corresponding physical processor cell operand memory addresses for a multi-dimensional processor array having at least one physical dimension that differs from a corresponding multi-dimensional problem dimension selectable from a plurality of multi-dimensional problem dimensions, comprising:
- a multi-dimensional processor array including a predetermined number of physical processor cells arranged in a multi-dimensional array having predetermined dimensions, each physical processor cell having a predetermined amount of associated memory;
- means for providing said plurality of selectable multi-dimensional problem dimensions;
- means, responsive to the means for providing the plurality of selectable multi-dimensional problem dimensions and to the predetermined number of physical processor cells arranged in said multi-dimensional array having said predetermined dimensions, for assigning, for each dimension of said plurality of selectable multi-dimensional problem dimensions, a number of virtual processors to be associated with each of said predetermined number of physical processor cells, and for arranging, for each physical processor cell, said number of virtual processors in a predetermined multi-dimensional configuration as a function of said plurality of selectable multi-dimensional problem dimensions and of the predetermined number of physical processor cells, and for forming a multi-dimensional array of virtual processor cells having a plurality of multi-dimensional dimensions corresponding to said plurality of selectable multi-dimensional problem dimensions;
- means, responsive to the means for assigning the number of virtual processors to be associated with each of said predetermined number of physical processor cells and to said arrangement of said number of virtual processors in a predetermined multi-dimensional configuration, for partitioning said predetermined amount of associated physical processor cell memory into a number of virtual processor memory segments corresponding to the number of virtual processors associated with each physical processor cell, for defining the address space of each virtual processor associated with each physical processor cell, and for defining, for each virtual processor, a physical processor cell memory address corresponding to a base virtual processor operand memory address defining the beginning operand memory address for each of said number of virtual processors associated with each physical processor cell;
- means for providing one or more processor cell instructions, each of said processor cell instructions including operand address data;
- means, responsive to said means for providing one or more processor cell instructions, for providing a virtual operand memory address for each operand to be processed by each virtual processor of said multi-dimensional array of virtual processors as directed by each processor cell instruction;
- means, responsive to said means for providing each of said virtual operand memory addresses and to said means for defining said virtual processor base memory addresses, for summing each virtual operand memory address with a virtual processor base memory address, to produce a physical processor cell address relocated operand memory address for directly addressing within each physical processor cell, each virtual processor operand to be processed, and for any given processor cell instruction requiring operand data movement, for providing for each address relocated operand memory address, a value indicating the relative physical processor cell distance to be moved in each dimension;
- means, responsive to said means for producing the physical processor cell address relocated operand memory address of each operand to be processed, and to said means for providing one or more processor cell instructions, for merging a processor cell instruction with a corresponding physical processor cell address relocated operand memory address, to produce an address relocated processor cell instruction to be broadcast to each virtual processor cell of the processor array.