Bus control system for arbitrating requests with predetermined on/off time limitations
AssigneeSilicon Graphics, Inc.
InventorSanjay Iyer
Life of this patent
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AssigneeSilicon Graphics, Inc.
InventorSanjay Iyer
Estimating the term…
A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.
A method of controlling the use of a computer bus, comprising the steps of:
A method of controlling the use of a computer bus, comprising the steps of:
An apparatus for controlling the use of a computer bus, comprising:
An apparatus for controlling the use of a computer bus, comprising:
Dependencies are inferred from the claim text.