Three-dimensional vector co-processor having I, J, and K register files and I, J, and K execution units

A processor capable of acting on a series of program instructions for carrying out vector/scalar, and scalar/vector arithmetic operations on three-dimensional vectors and scalar/scalar arithmetic operations, comprising

• a. a memory for storing the program instructions and data and for storing the results of arithmetic operations performed in accordance with the program instructions,
• b. a data-transfer input coupled to said memory for receiving the series of program instructions and data from the memory,
• c. I, J, and K register files coupled to said data-transfer input for receiving operands therefrom, each containing a plurality of registers for storing scalar values for the three vectors components of three-dimensional vectors,
• d. I, J, and K execution units coupled to said I, J, and K register files for performing arithmetic operations on operands placed in the execution units,
• e. I, J, and K operand pathways connecting each I, J, and K register file, respectively, with the corresponding I, J, and K execution unit, for transferring operands stored in selected register locations to the corresponding execution units, in response to data-fetch commands carried in the program instructions,
• f. first and second broadcast buffers connecting first and second parts of operand pathways, for passing operands between the two pathways in each pair, in response to pathway exchange commands carried in the program instructions,
• g. data-return means for returning operands from the execution units to selected locations in the register files, in response to write-to-register commands in the program instruction,
• h. a data-transfer output for passing selected operands to the memory, in response to write-to-memory commands carried in the program memory, and
• i. a program evaluation unit coupled to said I, J, and K register files for passing commands in the program instructions to the register files, the execution units, the broadcast buffers, the data-return means, and the data-transfer input and output.

A three-dimensional vector processing system for accelerating the computation of 3-D calculations without impairing the performance of other general-purpose operations, said system comprising:

• a system bus for carrying address, data, and control information;
• a general-purpose processor having an I/O interface coupled to said system bus and a general co-processor interface;
• a memory coupled to said system bus, said memory storing a series of program instructions and data;
• a co-processor coupled to said general-purpose processor and to said memory over said system bus for reading and processing said instructions and data under the control of said general-purpose processor, said co-processor further being coupled to said general-purpose processor over said general co-processor interface for synchronizing the execution of instructions targeted for said general-purpose processor and said co-processor, said co-processor further including:
• a. a data transfer input for receiving said series of program instructions and data from the memory;
• b. I, J and K register files coupled to said data transfer input for storing scalar values for the three scalar components of three-dimensional vectors in a plurality of registers;
• c. a source multiplexer coupled to said I, J and K register files for receiving operands therefrom;
• d. I, J and K execution units coupled to said source multiplexer for receiving resultant operands therefrom, said I, J and K execution units performing arithmetic and logical operations on said resultant operands stored in said execution unit;
• e. I, J and K operand pathways connecting each I, J and K register file, respectively, with the corresponding I, J and K execution unit, for transferring operands stored in selected register locations to the corresponding execution units, in response to data-fetch commands carried in the program instructions;
• f. a destination multiplexer coupled to said I, J, and K execution units for receiving processed operands therefrom, said destination multiplexer further changing the order of said processed operands, said destination multiplexer outputting selected operands;
• g. data-return means coupled to said destination multiplexer for receiving said selected operands therefrom, said data-return means further returning said selected operands to selected locations in said register files in response to receiving write-to-register commands in the program instruction,
• h. a data-transfer output coupled to said I, J and K register files for passing selected operands from the co-processor to the memory, in response to write-to-memory commands carried in the program instruction, and
• i. a control unit coupled between said system bus and said I, J and K register file for passing commands in said program instructions to said register files, said execution units, said source and destination multiplexers, said data-return means, and said data-transfer input and output.