Generalized 7/3 counters
AssigneeInternational Business Machines Corporation
InventorsStamatis Vassiliadis, Eric M. Schwarz
Life of this patent
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Abstract
A generalized 7/3 counter is proposed that may have all, some, or none of the input elements negative. The generalized counter can be used in array multipliers and in general for the reduction of matrices which have rows that must be added and need the advantage of a carry-free addition for speed purposes.
Claims9
A 7/3 counter for generating a three bit output including a sum bit (S), a first carry bit (C.sub.1), and a second carry bit (C.sub.2), such that C.sub.2 C.sub.1 S represents the difference between the number of positive, active bits and the number of negative, active bits in a seven-bit input including signed input bits x.sub.6 x.sub.5 x.sub.4 x.sub.3 x.sub.2 x.sub.1 x.sub.0, the counter including:
- EXCLUSIVE-OR means responsive to the seven-bit input for generating the sum bit according to:
- S=x.sub.0 Vx.sub.1 Vx.sub.2 Vx.sub.3 Vx.sub.4 Vx.sub.5 Vx.sub.6,
- where "V" denotes the EXCLUSIVE-OR logical operation;
- and
- logic means for combining a group of seven signed input bits to produce C.sub.1 and C.sub.2, the seven signed input bits having a first bit sign pattern which corresponds to a first range of possible sums of the seven bits or a second bit sign pattern which is the inverse of the first bit sign pattern and which corresponds to a second range of possible sums of the seven bits.
Dependencies are inferred from the claim text.