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US 5,187,604 AGranted
Multi-layer external terminals of liquid crystal displays with thin-film transistors
AssigneeHitachi, Ltd.
InventorsHideaki Taniguchi, Hirofumi Kunitou, Ryouji Oritsuki, Akira Sasano
Life of this patent
Estimating the term…
Abstract
An active matrix liquid crystal device is provided with improved external terminal structures including an ITO (indiumtin-oxide) pad covering an interconnection wiring, and a layout of a passivation film for protecting an aluminium wiring from outer moisture.
Claims13
A thin-film device comprising:
- a substrate;
- an external terminal for electrical connection with an external circuit;
- a first wiring including aluminum formed over said substrate;
- an insulating layer formed over said substrate and over said first wiring to cover substantially all of said first wiring, wherein said external terminal is not covered by said insulating layer;
- and
- a second interconnection wiring formed of a different material than said first wiring, said second wiring electrically connecting said first wiring with said external terminal, wherein said insulating layer covers a part of said second wiring so that a first portion of said second wiring is covered by said insulating layer and a second portion of said second interconnection wiring is not covered by said insulating layer so that said first wiring is electrically connected with said external terminal via said second wiring without being exposed from said insulating layer.
3 more elements
A thin-film device with a substrate over a principal surface of which is laminated a thin-film structure comprising:
- a plurality of thin-film transistors each including a gate, a source and a drain;
- a plurality of signal interconnection lines each electrically connecting predetermined ones of said sources and drains of said transistors associated therewith;
- a first-level conducting film formed over said principal surface of said substrate;
- a second-level conducting film comprised of aluminum formed over said principal surface of said substrate;
- a plurality of gate interconnection lines electrically connecting said gates of said transistors associated therewith, wherein at least a portion of each of said gate interconnection lines is formed by said second-level conducting film;
- a third-level insulating film formed over said principal surface of said substrate to substantially completely cover said transistors and said second-level conducting film so that said transistors and said second-level conducting film are not exposed from said third-level insulating film;
- a plurality of gate external terminals which are not covered by said third-level insulating film;
- and
- a plurality of interconnection wirings which are formed at least partially of said first-level conducting film, wherein said interconnection wirings include a first portion covered with said insulating film and a second portion not covered by said insulating film so that each of said gate interconnection lines is electrically connected to each of said terminals via one of said interconnection wirings without being exposed from said insulating film.
6 more elements
A thin-film device with a substrate over a principal surface of which is laminated a thin-film structure comprising:
- a plurality of thin-film transistors each including a gate, a source and a drain;
- a plurality of gate interconnection lines each electrically connecting said gates of said transistors associated therewith;
- a first-level conducting film formed over said principal surface of said substrate;
- a second-level conducting film comprised of aluminum formed over said principal surface of said substrate;
- a plurality of signal interconnection lines electrically connecting predetermined ones of said sources and drains of said transistors associated therewith, wherein at least a portion of each of said gate interconnection lines is formed by said second-level conducting film;
- a third-level insulating film formed over said principal surface of said substrate to substantially completely cover said transistors and said second-level conducting film so that said transistors and said second-level conducting film are not exposed from said third-level insulating film;
- a plurality of signal external terminal which are not covered by said third-level insulating film;
- and
- a plurality of interconnection wirings which are formed at least partially of said first-level film, wherein said interconnection wirings include a first portion covered with said insulating film and a second portion not covered by said insulating film so that each of said signal interconnection lines is electrically connected to each of said terminals via one of said interconnection wirings without being exposed from said insulating film.
6 more elements
Dependencies are inferred from the claim text.