Differential amplifier with common-mode stability enhancement

A differential amplifier with a common-mode stability enhancement comprising:

• input means for providing first and second currents respectively into first and second nodes, respectively in response to positive and negative differences between first and second input signals, and for adjusting a magnitude of a common-mode component of said first and second currents in response to a common-mode feedback signal;
• output means coupled to said input means, for providing first and second output signals proportional respectively voltages at third and fourth nodes;
• common-mode feedback means coupled to said input means and to said output means, for sensing a common-mode voltage at said third and fourth nodes, and for providing said common-mode feedback signal in response to a difference between said common-mode voltage and a reference voltage;
• and
• differential load means coupled to said input means, for providing voltages at said first and second nodes proportional respectively to said first and second differential currents, and for coupling said first and second nodes respectively to said third and fourth nodes, comprising:
• a first transistor, having a first current electrode coupled to said first node, a control electrode coupled to said third node, and second current electrode coupled to a power supply voltage terminal;
• a second transistor having a first current electrode coupled to said second node, a central electrode coupled to said third node, and a second current electrode coupled to said power supply voltage terminal;
• a third transistor having a first current electrode coupled to said first node, a control electrode coupled to said fourth node, and a second current electrode coupled to said power supply voltage terminal;
• and
• a fourth transistor having a first current electrode coupled to to said second node, a control electrode coupled to said fourth node, and a second current electrode coupled to said power supply voltage terminal.

A differential load for receiving differential currents at first and second nodes and for providing differential output voltages at third and fourth nodes comprising:

• a first transistor having a first current electrode coupled to the first node, a control electrode coupled to the third node and a second current electrode coupled to a power supply voltage terminal;
• a second transistor having a first current electrode coupled to the second node, a control electrode coupled to the third node and a second current electrode coupled to said power supply voltage terminal;
• a third transistor having a first current electrode coupled to the first node, a control electrode coupled to the fourth node and a second power current electrode coupled to said power supply voltage terminal;
• a fourth transistor having a first current electrode coupled to the second node, a control electrode coupled to the fourth node and a second current electrode coupled to said power supply voltage terminal;
• a first cascode element for coupling the first node to the third node to increase an output impedance at the third node;
• and a second cascode elements for coupling the second node to the
• fourth node to increase an output impedance at the fourth node.

A differential amplifier with common-mode stability enhancement comprising:

• input means for providing first and second differential currents respectively to first and second nodes, respectively in response to positive and negative differences between first and second input voltages, a magnitude of said first and second differential currents proportional to a common-mode feedback signal;
• differential load means providing first and second differential voltages proportional to said first and second differential currents, respectively;
• output means coupled to said input means and to said load means, for providing first and second output signals proportional to said first and second differential voltages, respectively;
• and
• common-mode feedback means, for sensing a common-mode voltage at said first and second nodes, and for providing said common-mode feedback signal proportional to the difference between said sensed common-mode voltage and a reference voltage;
• said differential load means comprising:
• a first transistor having a first current electrode coupled to said first node, a control electrode coupled to said first current electrode thereof, and a second current electrode coupled to a power supply voltage terminal;
• a second transistor having a first current electrode coupled to said second node, a control electrode coupled to said first current electrode of said first transistor, and a second current electrode coupled to said power supply voltage terminal;
• a third transistor having a first current electrode coupled to said first node, a control electrode coupled to said second node, and a second current electrode coupled to said power supply voltage terminal;
• and
• a fourth transistor having a first current electrode coupled to said second node, a control electrode coupled to said first current electrode thereof, and a second current electrode coupled to said power supply voltage terminal.

A differential amplifier with common-mode stability enhancement comprising:

• an input stage having first and second input terminals respectively receiving first and second voltages thereon, and first and second output terminals respectively coupled to first and second nodes and providing first and second currents respectively thereinto;
• a differential load having first and second input terminals respectively coupled to said first and second nodes, and first and second output terminals respectively providing third and fourth voltages to third and fourth nodes, said differential load comprising:
• a first transistor, having a first current electrode coupled to said first node, a control electrode coupled to said third node, and a second current electrode coupled to a power supply voltage terminal;
• a second transistor having a first current electrode coupled to said second node, a control electrode coupled to said third node, and a second current electrode coupled to said power supply voltage terminal;
• a third transistor having a first current electrode coupled to said first node, a control electrode coupled to said fourth node, and a second current electrode coupled to said power supply voltage terminal;
• and
• a fourth transistor having a first current electrode coupled to said second node, a control electrode coupled to said fourth node, and a second current electrode coupled to said power supply voltage terminal.