Multichip module and integrated circuit substrates having planarized patterned surfaces

A method of filling dielectric features in a substrate to produce a substantially planar patterned surface on said substrate, comprising the steps of:

• providing a substrate having a surface containing a pattern of features defined by a dielectric material;
• depositing a conductor layer on the surface of said substrate such that first portions of said conductor layer cover said dielectric material, second portions of said conductor layer fill said features, and said first and second portions are connected by thin sidewall portions of said conductor layer;
• coating said conductor layer with a resist and patterning said resist with a resist pattern similar to said pattern of features so that the resulting resist pattern extends over the second portions, sidewall portions, and a part of the first portions adjacent the sidewall portions;
• etching away said conductor layer except for said second portions filling said features, under conditions such that lateral etching of said sidewall portions of said conductor layer is inhibited by the resist pattern that extends over a part of the first portions adjacent the sidewall portions;
• and
• stripping said resist to produce a substantially planar patterned surface formed of the dielectric material and conductor layer second portions.