Method and apparatus for testing an analog to digital converter

A method of testing an analog to digital converter (ADC) comprising a plurality of resistors connected in series to form a resistor array with a first end and a second end, the method comprising the step of:

• performing a test that does not require an analog to digital conversion, the test further comprising the steps of:
• placing the analog to digital converter (ADC) in a special test mode;
• writing a value into a storage means;
• using the value to determine which portion of the resistor array to couple to an output signal;
• placing a first digital voltage level on the first end of the resistor array;
• and
• comparing the first digital voltage level of the first end of the resistor array to a second digital voltage level of the output signal to produce a comparison result.

Test apparatus for testing circuitry in an analog to digital converter (ADC) which has a plurality of resistors connected in series to form a resistor array with a first end and a second end, the test apparatus comprising:

• first logic means coupled to the first end of the resistor array, for applying an analog voltage level to the first end of the resistor array when the ADC is not in a special test mode, and for applying a first digital voltage level to the first end of the resistor array when the ADC is in the special test mode;
• second logic means coupled to at least two of the plurality of resistors for selectively coupling a portion of the resistor array to an output signal having a second voltage level which is analog when the ADC is not in the special test mode and which is digital when the ADC is in the special test mode;
• third logic means used only in the special test mode, coupled to the second logic means and the first end of the resistor array, for comparing the first voltage level of the first end of the resistor array to the second voltage level of the output signal for producing a comparison result;
• fourth logic means coupled to the third logic means for transmitting the comparison result outside of the analog to digital converter (ADC);
• a storage means for receiving and storing a digital value that determines which of the plurality of resistors will be included in the portion of the resistor array that is coupled to the output signal by the second logic means;
• and
• a control means coupled to the third logic means for enabling the third logic means to compare the first voltage level to the second voltage level.