Telephone communication system having an enhanced timing circuit

A signal synthesizing and monitoring circuit comprising:

• (a) primary signal synthesizing circuit comprising:
• (i) primary selector means, fed by a primary clock signal and a secondary clock signal, for coupling, in response to a primary control signal, either the primary clock signal or the secondary clock signal to an output thereof selectively in response to the primary control signal;
• and
• (ii) means, responsive to the selected one of either the primary clock signal or the secondary clock signal, for generating a plurality of primary frequency synthesized output signals, each one of said plurality of output signals having a different frequency;
• (b) secondary signal synthesizing and monitoring circuit comprising:
• (i) secondary selector means, fed by said primary clock signal and at least one of said plurality of primary frequency synthesized output signals, for coupling in response to a secondary control signal, either said primary clock signal or said at least one primary frequency synthesized output signal to an output thereof selectively in response to the secondary control signal;
• and
• (ii) a phase-locked loop circuit, responsive to the selected one of either the primary clock signal or the at least one primary frequency synthesized output signal, for generating a plurality of secondary frequency synthesized output signals, each one of said plurality of secondary output signals having a corresponding one of said frequencies, and for producing a selector control signal in accordance with the presence or absence of an error in the frequency of the selected one of either the primary clock signal or the at least one primary frequency synthesized output signals;
• (c) output selector means, fed by said plurality of primary frequency synthesized output signals and said plurality of secondary frequency synthesized output signals, for coupling, in response to an output control signal, either of said pluralities of output signals to a plurality of outputs thereof;
• and
• (d) control means, responsive to said selector control signal, for generating said primary control signal, said secondary control signal, and said output control signal.

A digital loop carrier system coupled between a plurality of subscribers and central office equipment, said digital loop carrier system comprising:

• a plurality of line cards, each one of said cards corresponding to at least one of the plurality of subscribers and adapted for being coupled thereto;
• a multiplexer/demultiplexer switch coupled to said plurality of line cards;
• a plurality of transmission formatting/de-formatting circuits coupled to said multiplexer/demultiplexer switch and adapted for coupling to said central office equipment;
• and
• a control circuit and a timing circuit, each of said control and timing circuits being coupled to said plurality of line cards, said multiplexer/demultiplexer switch, and said plurality of transmission formatting/de-formatting circuits, wherein said timing circuit comprises signal synthesizing means, responsive to an input reference clock signal, for generating a first plurality of frequency synthesized output signals, each one of said first plurality of output signals having a different frequency;
• and monitoring means including a phase-locked loop circuit, coupled to the signal synthesizing means, for providing at an output of such phase-locked loop circuit, a control signal indicating the deviation of the frequency of the at least one of the plurality of frequency synthesized output signals from a reference frequency.

A method of operating a system comprising the steps of:

• producing, in response to a first input signal, a plurality of primary output signals having different frequencies;
• producing, in response to a second input signal, a plurality of secondary output signals having said different frequencies;
• monitoring a primary clock signal and/or a selected one of the plurality of primary output signals with a phase-locked loop circuit to determine the presence or absence of an error in the frequency of a primary clock signal and/or a selected one of the plurality of primary output signals;
• and
• coupling, to outputs of the system, in the absence of an error in the frequency of the primary clock signal and the selected one of the plurality of primary output signals, the plurality of primary output signals and, concurrently therewith, providing the primary clock signal as the first input signal.

A circuit comprising:

• selector means, fed by a first signal and a second signal, for coupling said first signal to an output of said selector means during a first period of time and said second signal to said output during a second period of time;
• monitoring means, responsive to the signal coupled to the output of the selector means, for determining the presence or absence of an error in the frequency of said first signal during said first period of time and the presence or absence of an error in the frequency of said second signal during said second period of time;
• and
• signal synthesizing means, responsive to an input signal, for producing, at one of a pair of outputs thereof, said first signal, and wherein said selector means includes means for dividing, during said first time period, the frequency of the first signal by a factor corresponding to the one of the pair of outputs of said signal synthesizing means where said first signal is produced.