Switching system

A switching system for a cell of a fixed length having plural units of data, at least one unit including a header portion and remaining units including a data portion, the cell being inputted to a first incoming highway of incoming highways, to exchange communication information between the first incoming highway and a first outgoing highway of plural outgoing highways based upon information contained in said header portion, comprising:

• first switching means including a plurality of input terminals and a plurality of output terminals, a first input terminal of said input terminals being connected to the first incoming highway, for sequentially connecting each of the input terminals to each of the output terminals for every one unit of the data in the fixed length cell, and for continuously outputting data at predetermined bit positions of the plurality of output terminals;
• a plurality of memory means for storing data from said plural output terminals of said first switching means in response to a write address, and for reading the stored data in response to a read address;
• address generating means for outputting said write address and read address in response to the header portion of the cell outputted from said first switching means;
• shift means for applying the write address derived from said address generating means to said plurality of memory means while timing said first shift means application of the continuous output of data of the cell such that the plural units of data of the cell appearing on the first incoming highway are written at an identical address at each of said plurality of memory means;
• second switching means including a plurality of input terminals connected to each of corresponding outputs of said plurality of memory means, and a plurality of output terminals corresponding to the plural outgoing highways, for sequentially connecting each of the input terminals to each of the plurality of output terminals to output every unit of data of the cell from each of said plurality of memory means to said first outgoing highway of said plurality of outgoing highways through a first output terminals.

An m-input and n-output switching system for a cell of a fixed length in a k unit having a header portion and a data portion, (m, n, k each being integer), the cell inputted to each of incoming highways, to exchange communication information between m incoming highways (m.ltoreq.k) and n outgoing highways (n.ltoreq.k) based upon information contained in said header portion, comprising:

• first counter means for counting a first count value from "0" to (k-1), wherein k is a number of memories, at a predetermined first timing, and for returning the first count value to "0" in case of (k-1) and further for repeating the first counting operation;
• a first rotation matrix having m input terminals connected to said m incoming highways and k output terminals, for outputting data on a cell of a i-th ("i" being an integer, 0.ltoreq.i.ltoreq.(m-1)) incoming highway to an (i+j)-th output terminal when a value j ("j" being an integer, 0.ltoreq.j .ltoreq.(k-1) of said first counter means is in a range of (i+j) .ltoreq.(k-1), and to a (i+j-k)-th output terminal when a value j is in the range of (i+j).gtoreq.k;
• second counter means for counting up a second count value from "0" to (k-1) at a predetermined second timing, and for returning the second count value to "0" in case of (k-1), and also for repeating such a second counter operation;
• a second rotation matrix having k input terminals and output terminals connected to each of said "n" outgoing highways, for outputting cell data in an i-th (0.ltoreq.i.ltoreq.(k-1)) input terminal to (i-p)-th output terminal when a value p ("p" being an integer, 0.ltoreq.p.ltoreq.(k-1)) of said second counter means is in a range of a value p is (i+p).gtoreq.0, and to an (i-p+k)-th output terminal when in a range of (i-p)<0;
• "k" memory means whose inputs are connected to said k output terminals of the first rotation matrix and whose output are connected to said k input terminals of said second rotation matrix;
• memory control means for inputting information of the header portion among the data outputted from said first rotation matrix, for outputting a write address to a first memory means in response to said information, and for outputting the read address to the first memory means in response to the count value of said second counter means;
• (k-1) of first shift registers for inputting the write address therein which is inputted into a write address input of said (i-1)-th memory means, and for outputting the write address to a write address input of the i-th memory means;
• and,
• (k-1) second shift registers for inputting the read address therein which is inputted into a read address input of said (i-1)-th memory means, and for outputting the read address to a read address input of the i-th memory means.

A switching system for employing a cell of a fixed length having plural units of data, at least one unit including a header portion and remaining units including a data portion, which is inputted to each of incoming highways, so as to exchange communication information between plural incoming highways and plural outgoing highways based upon information contained in said header portion, comprising:

• first switching means including a plurality of input terminals and a plurality of output terminals, said input terminals being connected to the corresponding incoming highways, for sequentially connecting each of the input terminals to one of different output terminals for every one unit of data in the input cell, and for continuously outputting the data units at bit positions corresponding data position of respective incoming highways from the respective output terminals;
• a plurality of memory means for storing the data from said plural output terminals of said first switching means in response to a write address, and for reading the stored data in response to a read address;
• storage means for storing an empty address of an empty storage location of said plurality of memory means;
• address generating means for generating said write address and read address in accordance with the empty address in said storage means;
• first shift means for applying the write address derived from said address generating means to said plurality of memory means while timing the application of the write address to said plurality of memory means are for each one unit of the data of the cell such that the respective data each having 1 unit on the cell appearing on an incoming highway is written at the same address of said plurality of memory means;
• second switching means including both a plurality of input terminals connected to each of corresponding outputs of said memory means, and a plurality of output terminals corresponding to the respective outgoing highways, for sequentially connecting each of the input terminals to each of the different output terminals for every unit on the cell outputted from said memory means;
• and for outputting the data of the cell on the corresponding outgoing highways to the respective output terminals;
• and,
• second shift means for applying the read address derived from said address generating means to said plurality of memory means while timing application of the read address to said plurality of memory means are for every one unit of data respectively such that the data on the cells read out from said plurality of memory means are outputted from the second switching means as data on cells appearing in the respective outgoing highways.