Semiconductor memory device having on-chip test circuit and method for testing the same

A method of testing a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines arranged to intersect said word lines and a plurality of memory cells at intersections of said word lines and said bit lines, comprising the steps of:

• sequentially selecting said word lines and, in response, grouping memory cells of said selected word lines into two groups;
• testing memory cells of one of said groups for each sequentially selected word line in a line mode and detecting possible failures in memory cells connected to selected word lines;
• identifying a bit line included in said one group with word lines containing a memory cell failure to produce correlation data;
• and
• monitoring said correlation data to identify at least one bit line failure.

In a semiconductor memory device including a plurality of word lines, a plurality of bit lines arranged to intersect said word lines, and a plurality of memory cells at intersections of said word lines and said bit lines, a method of testing said semiconductor memory device comprising the steps of:

• testing successive word lines in a line mode wherein all memory cells connected to a word line under test are grouped into one of two groups of bit lines and tested simultaneously, said bit lines selectively grouped in response to selection of a word line for testing;
• identifying bit lines of each of said groups corresponding to said word lines being tested;
• and
• generating a signal identifying a location or locations of at least one bit line failure.

In a semiconductor memory device including, on a common chip, a plurality of word lines and bit lines arranged to intersect said word lines, and a plurality of memory cells at intersections of said word lines and said bit lines, a method of testing said semiconductor memory device comprising the steps of:

• supplying a sequence of row address signals specifying a succession of addresses;
• decoding said row address signals to supply a decoded address signal;
• sequentially selecting said word lines in response to said decoded address signal and successively assigning and bit lines to first and second groups;
• detecting a faulty memory cell in said first group and no faulty memory cell in said second group in response to said step of sequentially selecting said word lines;
• detecting no faulty memory cells in said first group and a faulty memory cell in second group in response to said step of sequentially selecting said word lines;
• and
• determining a location of a faulty column of said memory cells in response to said detecting steps.