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AssigneeSiemens Aktiengesellschaft
InventorsKurt Hoffmann, Rainer Kraus, Oskar Kowarik
Estimating the term…
An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.
Integrated semiconductor memory of the DRAM type, comprising word lines, bit line pairs, memory cells in a matrix being connected to said word lines and said bit lines, a plurality of sense amplifiers, each sense amplifier being connected to a respective bit line pair, each of said bit line pairs being divided into one bit line and one reference bit line, a control line, at least one first coupling capacitor for each of said bit lines, and at least one second coupling capacitor for each of said reference bit lines, each of said coupling capacitors having a first lead connected to a respective line of said bit line pairs and a second lead connected to said control line, means for applying a fixed potential to said control line when operating said semiconductor memory in a normal operating mode, and means for applying via said first and second coupling capacitor a test signal to said bit line pairs when operating said semiconductor memory in a test operating mode.
Integrated semiconductor memory of the DRAM type, comprising word lines, bit line pairs, memory cells in a matrix being connected to said word lines and said bit lines, a plurality of sense amplifiers, each of said sense amplifiers being connected to a respective bit line pair, each of said bit line pairs being divided into one bit line and one reference bit line, a control line, at least one first coupling capacitor for each of said bit lines and at least one second coupling capacitor for each of said reference bit lines, each of said coupling capacitors having first leads connected to a respective line of said bit line pair and second leads connected commonly to said control line, means for applying an electrical potential to said control line when operating said semiconductor memory in a normal operating mode, and means for applying a test signal to said control line when operating said semiconductor memory in a test mode.
Method for testing an integrated semiconductor memory of the DRAM type, which comprises precharging bit line pairs to a precharge potential, said precharge potential having a value being an optimum value with respect to operating conditions of said sense amplifier, coupling an additional potential to each bit line pair after precharging, reading out data stored in memory cells and sensing and amplifying said data after reading out.
Dependencies are inferred from the claim text.