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US 5,184,324 AGranted
Dynamic semiconductor multi-value memory device
AssigneeSharp Kabushiki Kaisha
InventorYoshiji Ohta
Life of this patent
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Abstract
A dynamic semiconductor multi-value memory device has memory cells each of which includes a series circuit of one storage capacitor and two transistors. A first capacitor is connected between a first bit line of a first bit line pair and a second bit line of a second bit line pair which is adjacent to the first bit line pair. A second capacitor is connected between a second bit line of the first bit line pair and a first bit line of the second bit line pair.
Claims4
In a dynamic semiconductor memory device comprising:
- memory cells each for storing multi-value data;
- and a plurality of bit line pairs of first and second bit lines, said first and second bit lines being complementary to each other, said memory device further comprises:
- first capacitor means connected between the first bit line of one of said bit line pairs and the second bit line of another one of said bit line pairs, said other one bit line pair being adjacent to said one bit line pair;
- and
- second capacitor means connected between the second bit line of said one bit line pair and the first bit line of said other one bit line pair.
2 more elements
Dependencies are inferred from the claim text.