Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement

A semiconductor device comprising:

• a semiconductor chip having long and short sides
• a plurality of memory arrays formed on said chip and arranged in a direction parallel to the long side of said chip,
• a memory drive means comprising a peripheral circuit for selectively driving said memory arrays over a plurality of column select lines running parallel to said long side of said chip, the widths of said column select lines being less than the widths of corresponding columns of memory cells in said arrays thereby providing spaces between said column select lines, said memory arrays in response to control signals applied to said driving means, said memory drive means being centrally located among said plurality of memory arrays,
• connection means for providing said control signals directly to said peripheral circuit, and
• power/ground connection means provided in said spaces between said column select lines for supplying power to said memory drive means,
• whereby a dimension of said semiconductor chip in the direction of the short side thereof is reduced.

A semiconductor memory device comprising:

• a rectangular substrate having long and short sides,
• a memory cell array comprising a plurality of memory cells formed on said substrate and disposed in a matrix of rows parallel to said short sides and columns parallel to said long sides, said memory cell array being divided into a plurality of columns such that a plurality of spacings are provided between said plurality of memory cells groups, each of said plurality of memory cells comprising one MOS transistor having a gate electrode and one storage means, said gate electrodes of said MOS transistors located at each row forming a first word line formed on a first layer over said rectangular substrate,
• a plurality of bit lines provided corresponding to said columns and each connected to the memory cells on the corresponding column, said plurality of bit lines being formed on a second layer over said rectangular substrate,
• a plurality of second word lines provided corresponding to said first word lines and each connected to the corresponding first word line at said spacings, said plurality of second word lines being formed of material having lower resistance than that of said first word lines and being formed on a third layer over said rectangular substrate,
• a plurality of column selecting lines disposed at said columns and formed on a fourth layer over said rectangular substrate so as to cross said memory cell array,
• a pad formed at one short side of said rectangular substrate and one end of said memory cell array and receiving a predetermined potential or signals, and
• an interconnection line formed on said fourth layer at one of said spacings and electrically connected to said pad so as to cross said memory cell array.

A semiconductor memory device comprising:

• a semiconductor substrate having long and short sides,
• a memory cell array comprising a plurality of memory cells formed on said substrate and arranged in a plurality of columns parallel to said long sides and a plurality of rows parallel to said short sides,
• a plurality of word lines provided corresponding to said plurality of rows and each connected to the memory cells belonging to the corresponding row,
• said plurality of word lines being formed on a first layer over said substrate,
• a plurality of bit line pairs provided corresponding to said plurality of columns and each connected to the memory cells belonging to the corresponding column,
• said plurality of bit line pairs being formed on a second layer over said substrate,
• a plurality of column selecting lines provided corresponding to said plurality of columns and each for selecting the bit line pair belonging to the corresponding column;
• said plurality of column selecting lines being formed on a third layer over said substrate so as to cross said memory cell array,
• one or more pads provided on one of said short sides and on one side of said memory cell array on said substrate and for receiving predetermined potentials or signals, and
• one or more interconnection lines provided between said plurality of column selecting lines in said third layer so as to cross said memory cell array and electrically connected to said pads.

A semiconductor device comprising:

• a semiconductor chip,
• a first memory array provided on said semiconductor chip and formed of predetermined layers,
• a second memory array provided on said semiconductor chip and formed of predetermined layers,
• driving circuit means comprising a peripheral circuit provided on said semiconductor chip for driving said first and second memory arrays over a plurality of column select lines, the widths of said column select lines being less than the widths of corresponding columns of memory cells in said first and second memory arrays thereby providing spaces between said column select lines,
• said first and second memory means being arranged on one and the other sides of said driving circuit means, respectively,
• one or more pads provided on said semiconductor chip for receiving externally applied signals and predetermined potentials, and
• interconnecting means, including interconnections formed of a layer other than said predetermined layers, for interconnecting said pads and said driving circuit means,
• said interconnections being provided in said spaces between column select lines so as to cross one of said first and second memory means, whereby no additional chip area is required to form said interconnections.

A semiconductor memory device comprising:

• a semiconductor chip,
• a first memory array provided on said semiconductor chip and formed of predetermined layers, said first memory means includes a first memory array,
• second memory means provided on said semiconductor chip and formed of predetermined layers, said second memory means includes a second memory array,
• each of said first and second memory arrays is divided with predetermined spacings into a plurality of blocks so as to divide each of a plurality of word lines at a plurality of points,
• driving circuit means comprising a peripheral circuit provided on said semiconductor chip for driving said first and second memory means,
• said first and second memory means being arranged on one and the other sides of said driving circuit means, respectively,
• one or more pads provided on said semiconductor chip for receiving externally applied signals and predetermined potentials, and
• interconnecting means, including interconnections formed of a layer other than said predetermined layers, for interconnecting said pads and said driving circuit means,
• said interconnections being provided so as to cross said first and second memory arrays in said predetermined spacings between said plurality of blocks, whereby no additional chip area is required to form said interconnections.

A semiconductor memory device comprising:

• a semiconductor substrate having first and second memory array forming regions arranged with a space therebetween and a circuit means forming region located in said space between said first and second memory array forming regions;
• a plurality of first memory cells formed in said first memory array forming region of said semiconductor substrate and arranged in a plurality of rows and columns, each including one transistor and one capacitive element;
• a plurality of first word lines arranged on said first memory array forming region of said semiconductor substrate, each connected to first memory cells arranged in a corresponding row;
• a plurality of first bit lines arranged on said first memory array forming region of said semiconductor substrate, each connected to first memory cells arranged in a corresponding column;
• a plurality of second memory cells formed in said second memory array forming region of said semiconductor substrate and arranged in a plurality of rows and columns, each including one transistor and one capacitive element;
• a plurality of second word lines arranged on said second memory array forming region of said semiconductor substrate, each connected to second memory cells arranged in a corresponding row;
• a plurality of second bit lines arranged on said second memory array forming region of said semiconductor substrate, each connected to second memory cells arranged in a corresponding column;
• circuit means formed in said circuit means forming region of said semiconductor substrate;
• an interconnection line electrically connected to said circuit means and arranged so as to cross one of said first and second memory array forming regions;
• and
• a plurality of first column selecting lines for selecting any of said plurality of first bit lines and a plurality of second column selecting lines for selecting any of said plurality of second bit lines;
• wherein
• said first and second memory array forming regions are arranged along the column direction,
• said circuit means includes first column selecting means receiving a column address signal and for selecting and activating any of said plurality of first column selecting lines and second column selecting means receiving a column address signal and for selecting and activating any of said plurality of second column selecting lines, and
• said interconnection line electrically connected to said circuit means is arranged between adjacent first or second column selecting lines.

A semiconductor memory device comprising:

• a semiconductor chip,
• a first memory means provided on said semiconductor chip and formed of predetermined layers;
• second memory means provided on said semiconductor chip and formed of predetermined layers;
• driving circuit means comprising a peripheral circuit provided on said semiconductor chip for driving said first and second memory means, said first and second memory means being arranged in a common column on one and the other sides of said driving circuit means, respectively;
• one or more pads provided on said semiconductor chip for receiving externally applied signals and predetermined potentials, said driving circuit means and the pads are all arranged in said common column;
• and
• interconnecting means, including interconnections formed of a layer other than said predetermined layers, for interconnecting said pads and said driving circuit means;
• wherein
• said interconnections are provided so as to cross one of said first and second memory means, whereby no additional chip area is required to form said interconnections,
• said first memory means includes a first memory array,
• said second memory means includes a second memory array,
• each of said first and second memory arrays includes a plurality of memory cells arranged in a plurality of columns and in a plurality of rows, a plurality of word lines provided corresponding to said plurality of rows and each connected to the memory cells belonging to the corresponding row, and a plurality of bit lines provided corresponding to said plurality of columns and each connected to the memory cells belonging to the corresponding column, and
• each of said first and second memory arrays is divided with predetermined spacings into a plurality of blocks so as to divide each of said plurality of word lines at a plurality of points;
• and
• further including
• column selecting lines formed in the same level on said chip as the layer including said interconnections, and
• a plurality of low resistance lines provided above said plurality of word lines in parallel thereto, each of said plurality of low resistance lines being connected to the corresponding word line at said plurality of points.

A semiconductor memory device comprising:

• a semiconductor substrate having first and second memory array forming regions arranged with a space therebetween and a circuit means forming region located in said space between said first and second memory array forming regions;
• a plurality of first memory cells formed in said first memory array forming region of said semiconductor substrate and arranged in a plurality of rows and columns, each including one transistor and one capacitive element;
• a plurality of first word lines arranged on said first memory array forming region of said semiconductor substrate, each connected to first memory cells arranged in a corresponding row;
• a plurality of first bit lines arranged on said first memory array forming region of said semiconductor substrate, each connected to first memory cells arranged in a corresponding column;
• a plurality of second memory cells formed in said second memory array forming region of said semiconductor substrate and arranged in a plurality of rows and columns, each including one transistor and one capacitive element;
• a plurality of second word lines arranged on said second memory array forming region of said semiconductor substrate, each connected to second memory cells arranged in a corresponding row;
• a plurality of second bit lines arranged on said second memory array forming region of said semiconductor substrate, each connected to second memory cells arranged in a corresponding column;
• circuit means formed in said circuit means forming region of said semiconductor substrate;
• and
• an interconnection line electrically connected to said circuit means and arranged so as to cross one of said first and second memory array forming regions;
• wherein
• said first and second memory array forming regions of said semiconductor substrate are arranged along the column direction,
• each of said plurality of first and second word lines has a first layer integrated with the gate electrodes of the transistors in memory cells arranged in a corresponding row and a second layer arranged above and parallel with said first layer with an insulator layer interposed therebetween, said second layer being electrically connected to said first layer at predetermined portions, and
• said interconnection line electrically connected to said circuit means is arranged so as to pass through connecting locations between first and second layers of said plurality of first or second word lines.