Fault simulation method

A fault simulation method for detecting a fault in a logic circuit comprising one or more logic gates having pins for data input and data output and functioning as an object of fault simulation, on the basis of logic simulation to be implemented by injecting a fault logic value into a position of fault assumption in the logic circuit, comprising the steps of:

• performing logical modification of the logic circuit into a logic circuit configuration including logic gates of a predetermined basic gate form;
• forming pin management data for the logic gates of the logic circuit after the logical modification which indicates correspondence of pins of the modified logic circuit to the position of fault assumption of each of the pins prior to the logical modification;
• injecting the fault logic value into the position of fault assumption of pins of the gate of the logic circuit subsequent to the logic modification in a position corresponding to each of the pins prior to the logic modification based on the pin management data;
• and
• executing fault simulation using the logic circuit into which the fault logic value is injected.