Switchable DAC with current surge protection
AssigneeAdvanced Micro Devices, Inc.
InventorsJimmy Fung, Jiu An, David L. Campbell, Steven Shyu
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AssigneeAdvanced Micro Devices, Inc.
InventorsJimmy Fung, Jiu An, David L. Campbell, Steven Shyu
Estimating the term…
In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.
In a digital-to-analog converter (DAC) having a plurality of stages, each of said stages having a current source coupled to a first and a second transistor which are operable as a differential pair, an apparatus for selectively switching said DAC between a normal operating mode and a sleep mode comprising:
In a digital-to-analog converter (DAC) having a plurality of stages, each of said stages having a current source coupled to a first and a second transistor which are operable as a differential pair, a method of operating said DAC in a normal operating mode and in a sleep mode comprising the steps of:
In a digital-to-analog converter (DAC) having a plurality of stages, each of said stages having a current source coupled to a reference voltage transistor and a data input transistor which are operable as a differential pair, an apparatus for selectively switching said DAC between a normal operating mode and a sleep mode comprising:
In a digital-to-analog converter (DAC) having a plurality of stages, each of said stages having a current source coupled to a reference voltage transistor and a data input transistor which are operable as a differential pair, an apparatus for selectively switching said DAC between a normal operating mode and a sleep mode comprising:
A digital-to-analog converter (DAC) having a plurality of stages, each of said stages having a current source MOS transistor coupled to a reference voltage MOS transistor and a data input MOS transistor, said DAC having a normal operating mode and a sleep mode, comprising:
Dependencies are inferred from the claim text.