Integrating A/D converter with means for reducing rollover error

In an integrating type A/D converter having an input pair of terminals for receiving an unknown analog input voltage signal having one of positive and negative polarity states, an integrator coupled to said input terminals for integrating the input voltage signal and then deintegrating the integrated signal against a reference voltage, and a comparator for comparing an output of said integrator to a predetermined reference level and providing an output of a zero crossing signal when the integrator output has reached said predetermined reference level,

• the improvement therewith comprising:
• switch means including a control logic unit connected to the output of said comparator, means for detecting the polarity state of the input voltage signal, and a set of analog switches having closed and open states which are settable by said control logic unit in response to detection of the polarity state of the input voltage signal, said switch means being operative for selectively coupling said input terminals to said integrator in order to apply, during an integrate phase, the input voltage signal for a predetermined period of time and in a polarity direction that causes said integrator to ramp up in the same polarity direction regardless of the polarity state of the input voltage signal, wherein an integrated signal is provided at the output of said integrator, and to apply, during a deintegrate phase, the reference voltage to said integrator in a polarity direction opposite to the ramp-up direction of said integrator in order to deintegrate said integrated signal to a predetermined level over a variable period of time corresponding to the amplitude of said integrated signal, whereupon said comparator provides a zero crossing signal to said control logic unit;
• and
• a pair of storage capacitors, one of which is connected by a switchable shunt path to the output of said integrator, and the other of which is connected in parallel with said shunt path between said integrator and said comparator, said storage capacitors having capacitances in a predetermined ratio to each other for feeding back to the integrator a residual voltage signal multiplied by the predetermined ratio in a second integrate/deintegrate phase, in order to measure a residual error in the detection of the zero crossing signal and produce a more accurate measurement of the deintegration time.

An integrating type A/D converter comprising:

• an input pair of terminals for receiving an unknown analog input voltage signal having one of positive and negative polarity states;
• a pair of reference voltage terminals for receiving reference voltages having predetermined high and low values, respectively;
• an input buffer having one input terminal for connection to one of a pair of input leads for an applied voltage, another input terminal connected in feedback connection to its output terminal, and its output terminal connected in series with one end of an integrating resistor;
• an integrator, including the integrating resistor and an integrating capacitor, having one input terminal for connection to the other of said pair of input leads for an applied voltage, another input terminal connected in common with the other end of said integrating resistor and one end of said integrating capacitor, said integrating capacitor having its other end connected to an output terminal of said integrator;
• a comparator having one input terminal connected to the output terminal of said integrator, a reference input terminal, and an output terminal;
• switch means including a control logic unit connected to the output terminal of said comparator, means for detecting the polarity state of the input voltage signal, and a set of analog switches having closed and opened states which are settable by said control logic unit in response to detection of the polarity of the input voltage signal, said switch means being operative for selectively connecting said pair of input terminals with said pair of input leads to said buffer and said integrator in order to apply, during an integrate phase, the input voltage signal across the pair of input leads for a predetermined period of time and in a polarity direction that causes said integrator to ramp up in the same polarity direction regardless of the polarity state of the input voltage signal, wherein an integrated signal is provided at the output terminal of said integrator and stored by said integrating capacitor, and during a deintegrate phase, a reference is applied across the input leads to said buffer and said integrator in a polarity direction opposite to the applied input voltage of said integrator in order to deintegrate said stored integrated signal to a predetermined level over a variable period of time corresponding to the amplitude of said integrated signal, wherein a zero crossing signal is provided at the output terminal of said comparator to said control logic unit;
• and
• said control logic unit having means, including a clock providing a series of clock pulses, and means for counting the clock pulses during the deintegration phase until said zero crossing signal is provided and for providing a digital representation of the analog input voltage signal corresponding to the counted clock pulses.