Sample-and-hold droop compensator for high speed high resolution analog-to-digital converter
AssigneeHughes Aircraft Company
InventorTerrence L. Myers
Life of this patent
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Abstract
A sample-and-hold droop compensation circuit including a ramp generator for producing a ramp signal synchronized with the hold timing of a sample-and-hold circuit and adjusted so as to tend to compensate the droop in the sample-and-hold output, circuitry for adding the ramp signal to the output of the sample-and-hold circuit to produce a sum signal, and a quantizer for providing a digital representation of the sum signal. The slope of the ramp signal is adjusted by a microcomputer by providing a reference input to the sample-and-hold circuit, determining the change in time of the sum signal, and adjusting the ramp signal so as to reduce the slope of the sum signal.
Claims5
A droop compensation circuit for compensating droop of a sample-and-hold circuit output, comprising:
- ramp generating means for producing a ramp signal synchronized with the hold timing of the sample-and-hold circuit;
- means for adding said ramp signal to the sample-and-hold circuit output to provide an analog sum signal, said ramp signal adjusted so as to tend to compensate the droop in the sample-and-hold circuit output;
- and
- quantizing means for providing a digital representation of said analog sum signal.
Dependencies are inferred from the claim text.