US 5,184,124 A · Method and apparatus for compressing and storing pixels

Abstract

A method and apparatus for a processor or other system device to map processor words to an associated random access memory. In one case, processor words are mapped directly to RAM with no modification. In another case, 32-bit pixels (eight bits each of red, green, blue and alpha) are converted to or from 16-bit pixels (four bits each of red, green, blue and alpha) using an ordered dithering technique. The ordered dithering technique spatially distributes the information that would otherwise be lost by truncation. This is accomplished by replacing exact pixel values with their pseudo-random average. This reduces the required pixel storage requirements by half, while maintaining a higher image quality than would be achieved by truncation alone.

Claims63

Dependent claims

A circuit comprising:

processing means for providing a memory address and a data word of a first number of bits;
storage means coupled to said processing means for storing said data word, said storage means having at least first and second address spaces;
address decoding means coupled to said processing means to determine if said memory address provided by said processing means is found in said first or second address space;
compression means coupled to said address decoding means, said processing means and to said storage means, said compression means for compressing said data word when said data word is written to said first address space.

1 more element

A circuit comprising:

processing means for providing a memory address and a data word of a first number of bits;
storage means coupled to said processing means for storing said data word, said storage means having at least first and second address spaces;
address decoding means coupled to said processing means to determine if said memory address provided by said processing means is found in said first or second address space;
compression means coupled to said address decoding means, said processing means and to said storage means, said compression means for compressing said data word when said data word is written to said first address space, said compression means comprising:
a matrix coupled to said processing means for receiving said memory address and for generating a threshold value based on said memory address;
a compression block coupled to said processing means and said matrix,
said compression block for receiving said threshold value and said data word and for providing an output value having a second number of bits less than said first number of bits, said compression block comprising:
first converting means for receiving said data word and for generating a BASE value based on said data word;
second converting means coupled to said first converting means for receiving said BASE value and said data word and for generating a DELTA value based on said BASE value and said data word;
first summing means for combining said DELTA value with said threshold value and providing a first output;
comparing means coupled to said first output and for generating a second output having a first value if said first output exceeds a reference value and a second value when said first output does not exceed said reference value;
second summing means for combining said BASE value and said second output and providing said output value having said second number of bits.

9 more elements

Dependencies are inferred from the claim text.

Method and apparatus for compressing and storing pixels

Life of this patent

Method and apparatus for compressing and storing pixels

Life of this patent

Abstract

Claims63