Method of manufacturing LDDFET having double sidewall spacers
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKatsuyoshi Mitsui, masahide Inuishi
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Abstract
In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.
Claims11
A method for manufacturing a MIS semiconductor device having a salicide structure and a LDD structure, said method comprising the steps of:
- forming a gate insulating film on a main surface of a semiconductor substrate;
- forming a uniform thickness of polysilicon on said gate insulating film;
- patterning said polysilicon of uniform thickness into a gate electrode of uniform thickness;
- introducing impurities into said semiconductor substrate using the patterned polysilicon gate electrode as a mask to form an impurity region with relatively low concentration;
- forming a first insulating film on the main surface of said semiconductor substrate and on the surface of said patterned polysilicon gate electrode;
- patterning said first insulating film to form a first sidewall spacer on a sidewall of said patterned polysilicon gate electrode by performing anisotropic etching of said first insulating film;
- introducing impurities into said semiconductor substrate using said polysilicon gate electrode and said first sidewall spacer as a mask to form an impurity region with relatively high concentration;
- then
- forming a second insulating film on the surface of said semiconductor substrate, said first sidewall spacer and said polysilicon gate electrode;
- patterning said second insulating film to form a second sidewall spacer on a sidewall of said first sidewall spacer by performing anisotropic etching on said second insulating film;
- and
- forming a refractory metal silicide layer on the surface of said semiconductor substrate and on an upper surface of said gate electrode.
A method for manufacturing a MIS semiconductor device having a salicide structure and a LDD structure, said method comprising the steps of:
- forming a gate insulating film on a main surface of a semiconductor substrate and patterning a polysilicon gate electrode on said gate insulating film to cover only a portion of the main surface of said semiconductor substrate;
- introducing impurities into portions of said semiconductor substrate uncovered by said gate electrode by using the patterned polysilicon gate electrode as a mask to form an impurity region with relatively low concentration;
- forming a first insulating film on the uncovered portions of said main surface of said semiconductor substrate and on the surface of said patterned polysilicon gate electrode;
- patterning said first insulating film to form a first sidewall spacer on a sidewall of said patterned polysilicon gate electrode by performing anisotropic etching of said first insulating film;
- introducing impurities into said semiconductor substrate using said polysilicon gate electrode and said first sidewall spacer as a mask to form an impurity region with relatively high concentration;
- then
- forming a second insulating film on the surface of said semiconductor substrate, said first sidewall spacer and said polysilicon gate electrode;
- patterning said second insulating film to form a second sidewall spacer on a sidewall of said first sidewall spacer by performing anisotropic etching on said second insulating film;
- and
- forming a refractory metal silicide layer on the surface of said semiconductor substrate and on an upper surface of said gate electrode.
Dependencies are inferred from the claim text.