Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt

In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which has a capability for detecting exception, interrupt, and trap events, including instruction exceptions, interrupt request, and execution traps of an internal interrupt instruction, said events having predefined priority levels, said data processor having a read-write memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events, a method for handling said events comprising:

• selecting an event among a plurality of detected events according to said priority;
• storing into said read-write memory a first information group that includes information indicative of the data processor internal state at the time said selected event is selected;
• storing into said read-write memory, under progrm control, a second information group that includes information indicative of a data processor internal state;
• fetching from said read-write memory, being the same read-write memory in which said first information group is stored, an entry address of an executable event handler corresponding to said selected event and said second information group in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group;
• and
• forming a new information group, using at least a part of said second information group, which is usable to define the data processor internal state at the time of starting executing of an executable event handler which has said fetched entry address to permit setting an internal state for each event handler.

In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting exception, interrupt, and trap events, said data processor including a device for storing a current processor status word for at least partially indicating the internal state of the data processor and having a read-write memory which receives address signals and control signals from said data processor, a method for handling said events, using stored event handlers, comprising:

• generating an address of a location in the read-write memory at which an indication of the start address of a process handler is stored;
• storing at least a part of a candidate processor status word in a location in said read-write memory, under program control;
• reading said part of a candidate processor status word from said location in said read-write memory, being the same read-write memory in which said indication of a start address is stored, said location being a predetermined distance from said generated address, wherein said reading is performed in response to the fetching of an EIT handler and in the absence of a separate instruction for fetching said candidate processor status word;
• comparing said current processor status word with said candidate processor status word and forming a new processor status word based on the results of said comparing;
• saving said current processor status word to a location in read-write memory;
• using said new processor status word to define a new internal state for said data processor to permit setting an internal state for each event handler;
• and
• starting an event handler while said data processor is in said new internal state.

In a data processor which can execute a plurality of instructions, and which has a capability for detecting exception, interrupt and trap events, including instruction exceptions, interrupt request signals and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:

• a read-write memory for storing data and instructions, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events;
• means, coupled to said read-write memory, for storing a first information group that includes information indicative of the data processor internal state;
• means, coupled to said read-write memory, for storing, under program control second and third information groups in said read-write memory, said second and third information groups being different from said first information group and being different from each other, said second and third information groups each including information indicative of a data processor internal state;
• means, coupled to said read-write memory, for holding an entry address of an executable event handler;
• means, coupled to said read-write memory, for selecting one of said second and third information groups;
• and
• means, coupled to said read-write memory, being the same read-write memory in which said first information group is stored, for fetching from said read-write memory said selected one of said second and third information groups to permit setting an internal state for each event handler in response to the fetching of said event handler and in the absence of a separate instruction for fetching said selected one of said second and third information groups.

In a data processor which can execute a plurality of instructions which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting an exception, interrupt, and trap events, including instruction exceptions, interrupt request signals, and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:

• a memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, said memory storing a plurality of fetchable, executable event handlers, each event handler being a sequence of instructions stored at memory locations starting at an entry address;
• means, coupled to said memory, for storing, in said memory, a first information group that includes information indicative of the data processor internal state, said information group including at least part of the information stored in said at least one control register;
• means, coupled to said memory, for holding an entry address of an executable event handler;
• means, coupled to said memory, for storing in said memory, under program control, a second information group, different from said first information group, that includes information indicative of a data processor internal state;
• and
• means, coupled to said at least one control register, for fetching from a memory which is not a read-only memory, and storing into said at least one control register, said second information group, in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group.