Data addressable memory architecture and method of forming a data addressable memory

A data addressable memory architecture, comprising:

• (a) separate bi-directional control, address and data buses;
• (b) a set of log, twist and linked list memories, each of said memories having a set of control ports, address ports and data ports, said log, twist and linked list memories having respective arrays of log, twist and linked list memory locations, each memory location capable of being enabled and controlled via said control ports, identified via said address ports and written into and read from via said data ports;
• and
• (c) control means connecting said set of control, address and data ports of each of said log, twist and linked list memories in different configurations with said separate bi-directional control, address and data buses for enabling and controlling identifying, writing and reading operations with respect to said log, twist and linked list memories;
• (d) a first of said connecting configurations of said control means making said log memory locations capable of being sequentially identified by different address values and of storing data values at least some of which can be identical;
• (e) a second of said connecting configurations of said control means making said twist memory locations capable of being sequentially identified by said data values and of storing said address values such that a subsequent one of said address values is permitted to over-write a previous one of said address values stored at the same one of said second memory locations identified by identical ones of said data values;
• (f) a third of said connecting configurations of said control means making said linked list memory locations capable of being sequentially identified by said address values and of storing said over-written address values such that said address values over-written at said twist memory locations, which identify log memory locations of said log memory where identical ones of said data values are stored, are preserved at said linked list memory locations.

A method of forming a data addressable memory architecture, comprising the steps of:

• (a) defining a plurality of first memory locations capable of being sequentially identified by different address values and of storing data values at least some of which can be identical;
• (b) defining a plurality of second memory locations capable of being sequentially identified by said data values and of storing said address values such that a subsequent one of said address values is permitted to over-write a previous one of said address values stored at the same one of said second memory locations identified by identical ones of said data values;
• and
• (c) defining a plurality of third memory locations capable of being sequentially identified by said address values and of storing said over-written address values such that said address values over-written at said second memory locations, which identify said first memory locations where identical ones of said data values are stored, are preserved at said third memory locations.