Direct memory access controller with adaptive pipelining and bus control features

A multi-channel DMA (Direct Memory Access) controller unit for controlling access to memory in a data processing system, via a system bus connectable to plural other device and controller units, said DMA controller unit and other units being required to arbitrate for access to said bus, said DMA controller unit containing plural internal channels for transferring data between said system memory and plural external devices having no direct connection to said bus and operating in asynchronous relation to said bus, said DMA controller unit comprising:

• internal memory means, said internal memory means containing storage spaces assigned to said internal channels for storing data in transit through respective channels, and additional storage spaces assigned to said internal channels for storing control information defining operations to be conducted relative to respective channels and said system memory;
• bus control means coupled to said system bus for arbitrating for and controlling said bus, and for operating through said bus to transfer data between said internal channels and said system memory;
• DMA control (DMAC) means containing respective DMAC buffer registers for storing data and control information relative to any one of said internal channels;
• said DMAC means being coupled to said internal memory means for transferring data and control information between said DMAC buffer registers and said internal memory means relative to one said internal channel at a time;
• said DMAC means including means for performing logical operations relative to individual ones of said internal channels that are defined by control information held in said DMAC buffer registers, said logical operations including operations for preparing said bus control means for gaining control of said system bus and for transferring data through said bus between an internal channel and said system memory;
• and
• DMA data buffer (DMADB) means containing respective DMADB buffer registers for holding data and control information associated with any one of said internal channels;
• said DMADB means interfacing between said bus control means and said DMAC means for transferring data and control information between its DMADB buffer registers and the DMAC buffer registers of the DMAC means, and for transferring data and control information between said DMADB buffer registers and said bus control means;
• said DMAC and DMADB means being capable of operating in a pipelined manner to sustain data transfer actions between said internal memory means and said bus control means relative to more than one internal channel at a time;
• said DMADB means and bus control means operating in tight coupled synchronism, and both operating in relative asynchronism to said DMAC means;
• so that while said DMAC means and said DMADB means are cooperating to prepare said DMADB means for a data transfer operation relative to one internal channels, said DMADB means and bus control means can be operating to conduct a data transfer operation between another internal channel and said system memory via said system bus.