Array layout structure for implementing large high-density address decoders for gate array memories

A semiconductor memory having an address decoder formed on a common substrate as the memory, the semiconductor memory including a matrix of bit lines and word lines extending in respective row and column directions and a plurality of memory cells at cross-overs of said bit and word lines, said word lines being uniformly spaced apart to have a predetermined first pitch, said address signal decoder comprising:

• a decoder matrix of first combinational logic devices arrayed in adjacent rows of logic circuit benches, said benches being substantially uniformly spaced in said column direction to have a predetermined second pitch, each bench including a plurality of basic cells uniformly spaced in said row direction to have said first predetermined pitch, each of said logic devices including a predetermined number of said basic cells including first and second input nodes and an output node connected to a respective word line;
• a first address signal subdecoder for receiving a first portion of an address signal and including a plurality of second combinational logic circuits formed outside said decoder matrix for supplying first subdecoded address signals;
• a plurality of first subdecoder signal lines arrayed in rows within said decoder matrix, said first subdecoder signal lines being substantially uniformly spaced in said column direction to have a pitch substantially equal to said second pitch, said first subdecoder signal lines receiving said first subdecoded address signals and being connected to said first input nodes of said combinational logic devices in respective rows;
• a second address signal subdecoder for receiving a second portion of said address signal and including a plurality of third combinational logic circuits formed outside said decoder matrix for supplying second subdecoded address signals;
• and
• a plurality second subdecoder signal lines arrayed in columns within said decoder matrix having a pitch equal to approximately four times said second pitch, said second subdecoder signal lines receiving said second subdecoded address signals and being connected to said second input nodes of said combinational logic devices in respective columns.

A semiconductor memory comprising:

• an array of n (wherein n is an integral multiple of 4) substantially uniformly spaced word lines extending in a column direction and m bit lines extending in a row direction substantially orthogonal to said column direction;
• a plurality of memory cells connected to respective ones of said word lines and said bit lines;
• and
• an address signal decoder including
• (i) a matrix of 16 combinational logic elements arranged in a square array having first through fourth rows and first through fourth columns, each of said combinational elements having a first and second input node and an output node connected to a respective one of said word lines;
• (ii) a first address signal subdecoder for receiving a first portion of an address signal and, in response, supplying respective first through fourth subdecoded address signals at respective first through fourth output nodes;
• (iii) a second address subdecoder for receiving a second portion of said address signal and, in response, supplying respective fifth through eighth subdecoded address signals at respective fifth through eighth output nodes;
• (iv) first through fourth subdecoder signal lines extending in said row direction from respective ones of said first through fourth output nodes of said first subdecoder to first terminals of said combinational logic elements in respective ones of said first through fourth rows;
• and
• (v) fifth through eighth subdecoder signal lines extending in said column direction from respective one of said fifth through eighth output nodes of said second subdecoder to second terminals of said combinational logic elements in respective ones of said first through fourth columns.

An address signal decoder for providing decoded address signals to respective word lines in response to an address signal, comprising:

• pluralities of first and second subdecoder output lines arrayed in rows and columns to form a plurality of matrices extending in a row direction;
• a rectangular column subdecoder for receiving a first portion of said address signal and supplying first subdecoded address signals to respective first subdecoder output lines;
• a plurality of rectangular row subdecoders formed outside said matrices and extending in said row direction, each for receiving a second portion of said address signal and each supplying second subdecoded address signals to respective second subdecoder output lines;
• and
• a plurality of first combinational logic elements, each having only two input nodes connected to corresponding first and second subdecoder output lines for responding to said first and second subdecoded address signals to supply decoded address signals to respective word lines.