Circuit and method for discharging a memory array

A circuit for discharging column lines of a memory array, comprising:

• a resistor, said resistor connected between a supply voltage and a common node, said resistor enabled by a program enable signal;
• at least one driver transistor of a first conductivity-type, said driver transistor having a source-drain path and a gate, said source-drain path of said driver transistor connected between a said column line and reference potential, said gate of said driver transistor coupled to said common node;
• an enabling transistor of said first conductivity-type, said enabling transistor having a source-drain path and a gate, said source-drain path of said enabling transistor connected between said reference potential and said common node, said gate of said enabling transistor connected to said program enable signal;
• at least one inverter, an OR circuit, and a bypass transistor of a second conductivity-type, said bypass transistor having a source-drain path and a gate, said source-drain path of said bypass transistor connected between said supply voltage and said common node, said gate of said bypass transistor coupled to said common node through said at least one inverter and said OR circuit, said program enable signal coupled to said OR circuit;
• a first transistor of said first conductivity-type, said first transistor having a source-drain path and a gate, said source-drain path of said first transistor connected between said gate of said driver transistor and said reference potential, said gate of said first transistor connected to a virtual ground signal;
• and
• a second transistor of said first conductivity-type, said second transistor having a source-drain path and a gate, said source-drain path of said third transistor connected between said gate of said driver transistor and said reference potential, said gate of said second transistor connected to said program enable signal;
• wherein said resistor is a third transistor of said second conductivity-type, said third transistor having a source-drain path and a gate, said source-drain path of said third transistor connected between a supply voltage and a common node, said gate of said third transistor connected to said program enable signal;
• wherein said source-drain path of said third transistor has a larger resistance than said source-drain path of said driver transistor;
• wherein said driver transistor is a N-channel transistor;
• and
• wherein said common node is coupled to said gate of said driver transistor by a fourth transistor of said second conductivity-type, said fourth transistor having a source-drain path and a gate, said source-drain path of said fourth transistor connected between said common node and said gate of said driver transistor, said gate of said fourth transistor connected to said virtual ground signal.