Nonvolatile semiconductor memory device with reduced variation in source potential of floating gate type memory transistor and operating method therefor

In a semiconductor device comprising an array of semiconductor components arranged in rows and columns and formed on a common substrate and wherein variations of substrate resistance among substrate regions between said components, due to distributed source resistance of a source interconnection layer, tends to undesirably vary operating characteristics of the components, and addressing means for addressing a particular one of said components from among said array of components, said addressing means including row addressing means responsive to an external row address for selecting a row of said array of components and column addressing means responsive to an external column address for selecting at least one column of said array of components,

• an improvement for reducing said substrate resistance variations, comprising:
• (a) switch means interconnecting each of said columns directly to a common reference potential source;
• and
• (b) control means responsive to said column addressing means for controlling said switch means to connect to said common reference potential source all said columns except said at least one column selected by said external column address and wherein said control means comprises inverting means for inverting an output of said column addressing means.

A nonvolatile semiconductor memory device comprising a plurality of memory elements each arranged at an intersection in a matrix of rows and columns for storing information in a nonvolatile manner, each of said memory elements having one conduction region connected to an associated column line and another conduction region, and conductor lines, formed in a source layer having a distributed resistance, each connecting respective other conduction regions of memory elements on a same row, comprising:

• ground lines provided at a predetermined number of memory elements on a row, for coupling to ground potential;
• row selecting means responsive to an external row address for selecting a row of said plurality of memory elements;
• column selecting means responsive to an external column address for selecting at least one column of said plurality of memory elements;
• and
• coupling means responsive to said external column address for coupling column lines of non selected columns, through said ground lines, to ground potential to reduce variations in source resistance and thereby equalize potential of each respective drain region of memory elements in a selected row.

A nonvolatile semiconductor memory device comprising a plurality of memory elements each arranged at an intersection in a matrix of rows and columns for storing information in a nonvolatile manner, each of said memory elements having a first conduction region connected to an associated column line and a second conduction region, second conduction regions of memory elements on a same row being connected together through a source layer having a distributed resistance, comprising:

• connection lines provided at a predetermined number of memory elements on a row, for coupling said second conduction regions to ground potential through said source layer with different respective resistances;
• row selecting means responsive to an external row address for selecting a row of said plurality of memory elements;
• column selecting means responsive to an external column address for selecting at least one column of said plurality of memory elements in a selected row;
• and
• coupling means responsive to said external column address for connecting, through a conductor line and a switching element, the first conduction region of each non selected memory element in said selected row directly to ground potential to reduce variations in source resistance and thereby equalize potential of each respective second conduction region of memory elements in a selected row.

A nonvolatile semiconductor memory device comprising:

• a plurality of semiconductor memory elements formed on a common substrate and arranged in a matrix of rows and columns for storing information in a nonvolatile manner;
• a plurality of word lines formed on the substrate in the row direction;
• row selection means responsive to an external row address for selecting a row of said plurality of memory elements;
• a plurality of bit lines formed on the substrate in the column direction;
• column selection means responsive to an external column address for selecting at least one column of said plurality of memory elements;
• said memory elements each including a memory transistor, the memory transistors of each row having source regions connected together in a source diffusion layer having a distributed resistance and formed on the substrate in parallel with the word lines, drain regions connected to respective column bit lines and gates connected to a respective word line;
• conductor lines at ground potential arranged in parallel direction to said bit lines and provided at a predetermined number of memory elements on a row each said source region connected to an associated conductor line through said source diffusion layer to provide different resistance with respect to said associated conductor line;
• and
• column coupling means responsive to said external column address for coupling the source regions of memory transistors not selected by said column selection means on a row selected by said row selection means directly to ground potential to reduce variations in source resistance and thereby equalize potential of each respective source region of memory transistors in the selected row.