Flicker reduction circuit for interlaced video images

A circuit which combines, for each horizontal line of video signal input, a plurality of prior adjacent lines of video signal input with a plurality of following adjacent lines of video signal input, where each line consists of a plurality of pixels, to produce a time division multiplexed analog video signal, and which converts said horizontal line of video signal input to an analog video signal, and which combines said time division multiplexed analog video signal with said analog video signal to produce an interlaced analog video signal output, said circuit comprising:

• processing means for receiving said plurality of prior adjacent lines of video signal input and said plurality of following adjacent lines of video signal input and providing therefrom a time division multiplexed signal comprising a plurality of time division units, where each of the time division units contains a portion of the video signal input corresponding to a single pixel within a single line selected from the group consisting of the prior and the following lines of video signal input, and where for each pixel position within said horizontal line of video signal input, corresponding pixels from said plurality of prior adjacent lines of video signal input and from said plurality of following adjacent lines of video signal input are contained in adjacent units of the time divisions;
• first digital to analog signal conversion means for receiving said time division multiplexed signal at a sampling rate sufficient for sampling of the time division units and delivering said time division multiplexed analog video signal, and including means for biasing the amplitude of said time division multiplexed analog video signal;
• second digital to analog signal conversion means for receiving said horizontal line of video signal input at a sampling rate sufficient for sampling of said horizontal line of video signal input and delivering said analog video signal, and including means for biasing the amplitude of said analog video signal;
• and
• combining means for combining said time division multiplexed analog video signal with said analog video signal and delivering the corresponding sum analog video signal output suitable for driving an interlaced video output device.

A flicker filter, comprising:

• a plurality of buffers for receiving digital video input signals, said video input signals formatted to correspond to a plurality of scan lines, each scan line including pixel data, said buffers each responsive to control signals for:
• storing said pixel data for a selected scan line provided at an input, and
• providing said pixel data at an output;
• a first digital-to-analog converter circuit, coupled to said output of one of said plurality of buffers and responsive to one of said control signals, for converting said pixel data of one particular scan line of said digital video input signals into analog signals, said first digital-to-analog converter circuit providing said converted pixel data at an output;
• a multiplexer, responsive to said one of said control signals and coupled to said output of a second one and a third one of said plurality of buffers, for routing a particular one of said pixel data of a selected one scan line of said second and third buffer to an output of said multiplexer;
• and
• a second digital-to-analog converter circuit, coupled to said output of said multiplexer and responsive to one of said control signals, for converting said particular one pixel data into analog signals, said second digital-to-analog converter circuit providing said converted digital video signals of said particular one pixel data an output of said second converter circuit coupled to said output of said first digital-to-analog converter circuit.

A flicker filter, comprising:

• a plurality of buffers for receiving digital video input signals, said video input signals formatted to correspond to a plurality of scan lines, each scan line including pixel data used for image development, said buffers each responsive to control signals for:
• storing pixel data of a selected scan line provided at an input, and;
• for providing said pixel data at an output, a first one of said buffers storing a field of pixel data and a second one of said buffers, having an input coupled to an output of said first one buffer, storing a line of said pixel data;
• a first digital-to-analog converter circuit, responsive to one of said control signals, for converting said pixel data of a first particular scan line of said digital video input signals into analog signals, said first digital-to-analog converter circuit providing said converted digital video signals at an output;
• a multiplexer, responsive to said one of said control signals and coupled to said output of said first one and an output of said second one of said plurality of buffers, for routing a particular one of said pixel data of a selected one scan line of said second and third line buffer to an output of said multiplexer;
• and
• a second digital-to-analog converter circuit, coupled to said output of said multiplexer and responsive to one of said control signals, for converting said particular one pixel data into analog signals, said second digital-to-analog converter circuit providing said converted digital video signals to said particular one pixel data an output of said second converter circuit coupled to said output of said first digital-to-analog converter circuit.

A flicker filter, comprising:

• a plurality of buffers for receiving digital video input signals, said video input signals formatted to correspond to a plurality of scan lines, each scan line including pixel data, said buffers each responsive to control signals for:
• storing said pixel data for a selected scan line provided at an input, and
• providing said pixel data at an output;
• a timing circuit, responsive to one of said control signals, for generation of a select signal and a clock signal;
• a multiplexer, coupled to said outputs of said buffers and responsive to said select signal, to successively route particular corresponding pixel data from said plurality of buffers to an output of said multiplexer in order to provide digital pixel information from at least two of said buffers during one output pixel period;
• and
• a digital-to-analog converter circuit, coupled to said multiplexer output and responsive to said clock signal, for converting said particular corresponding pixel data into analog signals.

A flicker filter, comprising:

• a plurality of buffers for receiving digital video input signals, said video input signals formatted to correspond to a plurality of scan lines, each scan line including pixel data used for image development, said buffers each responsive to control signals for:
• storing pixel data of a selected scan line provided at an input, and;
• for providing said pixel data at an output, a first one of said buffers storing a field of pixel data and a second one of said buffers, having an input coupled to an output of said first one buffer, storing a line of said pixel data;
• a timing circuit, responsive to one of said control signals, for generation of a select signal and a clock signal;
• a multiplexer, coupled to said output of said buffers and responsive to said select signal, to successively route particular corresponding pixel data from said plurality of buffers and an input receiving said digital video input to an output of said multiplexer in order to provide digital pixel information from at least one of said buffers and said input receiving said digital video input during one output pixel period;
• and
• a digital-to-analog converter circuit, coupled to said multiplexer output and responsive to said clock signal, for converting said particular corresponding pixel data into analog signals.

A method for producing output video signals from a plurality of digital video input signals formatted to produce a plurality of scan lines for an image development device, each scan line including a plurality of pixel data, comprising the steps of:

• converting a particular one of the plurality of scan lines to an analog output signal;
• time-division multiplexing corresponding pixel data from at least one more scan line to produce a time division multiplexed digital output, said one more scan line being adjacent to said particular one scan line;
• converting said time division multiplexed digital output to a time division multiplexed analog output signal;
• and
• merging said analog output signal with said time division multiplexed analog output signal.